pub struct HardwareCapabilities {
pub arch: TargetArch,
pub has_mpu: bool,
pub mpu_regions: u8,
pub has_pmp: bool,
pub pmp_entries: u8,
pub has_fpu: bool,
pub fpu_precision: Option<FPUPrecision>,
pub has_simd: bool,
pub simd_level: Option<SIMDLevel>,
pub xip_capable: bool,
pub flash_size: u64,
pub ram_size: u64,
}Expand description
Hardware capabilities
Fields§
§arch: TargetArchTarget architecture
has_mpu: boolHas Memory Protection Unit (MPU) for ARM
mpu_regions: u8Number of MPU regions (typically 8 or 16)
has_pmp: boolHas Physical Memory Protection (PMP) for RISC-V
pmp_entries: u8Number of PMP entries (up to 16)
has_fpu: boolHas Floating Point Unit
fpu_precision: Option<FPUPrecision>FPU precision
has_simd: boolHas SIMD/vector extensions
simd_level: Option<SIMDLevel>SIMD level
xip_capable: boolCan execute-in-place (XIP) from flash
flash_size: u64Flash size in bytes
ram_size: u64RAM size in bytes
Implementations§
Source§impl HardwareCapabilities
impl HardwareCapabilities
Sourcepub fn cortex_m4f_typical() -> Self
pub fn cortex_m4f_typical() -> Self
Create capabilities for a typical Cortex-M4F
Sourcepub fn stm32h743() -> Self
pub fn stm32h743() -> Self
Create capabilities for STM32H743 (Cortex-M7 with double-precision FPU)
16 MPU regions, 2MB Flash, 1MB RAM (DTCM + AXI SRAM + SRAM1-4).
Sourcepub fn imxrt1062() -> Self
pub fn imxrt1062() -> Self
Create capabilities for i.MX RT1062 (Cortex-M7 with single-precision FPU)
Representative high-end M7 with 16 MPU regions, single-precision FPU, large OCRAM, and external XIP-capable QuadSPI Flash. Matches the configuration of safety-grade lockstepped M7 platforms used in industrial and embedded automotive contexts.
Trait Implementations§
Source§impl Clone for HardwareCapabilities
impl Clone for HardwareCapabilities
Source§fn clone(&self) -> HardwareCapabilities
fn clone(&self) -> HardwareCapabilities
1.0.0 (const: unstable) · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more