pub struct SVerilogModule {
pub ports: Vec<SVerilogPortDef>,
pub defs: Vec<SVerilogWireDef>,
pub assigns: Vec<SVerilogAssign>,
pub cells: Vec<SVerilogCell>,
}Expand description
A parsed structural verilog module.
Fields§
§ports: Vec<SVerilogPortDef>Module ports.
defs: Vec<SVerilogWireDef>Module I/O and net definitions.
assigns: Vec<SVerilogAssign>Assignment operations in the module body.
cells: Vec<SVerilogCell>Cells in the module body.
Trait Implementations§
Auto Trait Implementations§
impl Freeze for SVerilogModule
impl RefUnwindSafe for SVerilogModule
impl Send for SVerilogModule
impl Sync for SVerilogModule
impl Unpin for SVerilogModule
impl UnwindSafe for SVerilogModule
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more
Source§impl<T> IntoEither for T
impl<T> IntoEither for T
Source§fn into_either(self, into_left: bool) -> Either<Self, Self>
fn into_either(self, into_left: bool) -> Either<Self, Self>
Converts
self into a Left variant of Either<Self, Self>
if into_left is true.
Converts self into a Right variant of Either<Self, Self>
otherwise. Read moreSource§fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
Converts
self into a Left variant of Either<Self, Self>
if into_left(&self) returns true.
Converts self into a Right variant of Either<Self, Self>
otherwise. Read more