pub struct SVerilogCell {
pub macro_name: Substr,
pub cell_name: Substr,
pub ioports: Vec<(Substr, Wirexpr)>,
}Expand description
A parsed cell instantiation in structural verilog.
Fields§
§macro_name: SubstrThe name of macro. E.g. NAND.
cell_name: SubstrThe name of cell. E.g. nand01.
ioports: Vec<(Substr, Wirexpr)>contains tuples of (macro_pin_name, wire_name).
Trait Implementations§
Source§impl Debug for SVerilogCell
impl Debug for SVerilogCell
Auto Trait Implementations§
impl Freeze for SVerilogCell
impl RefUnwindSafe for SVerilogCell
impl Send for SVerilogCell
impl Sync for SVerilogCell
impl Unpin for SVerilogCell
impl UnwindSafe for SVerilogCell
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more
Source§impl<T> IntoEither for T
impl<T> IntoEither for T
Source§fn into_either(self, into_left: bool) -> Either<Self, Self>
fn into_either(self, into_left: bool) -> Either<Self, Self>
Converts
self into a Left variant of Either<Self, Self>
if into_left is true.
Converts self into a Right variant of Either<Self, Self>
otherwise. Read moreSource§fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
fn into_either_with<F>(self, into_left: F) -> Either<Self, Self>
Converts
self into a Left variant of Either<Self, Self>
if into_left(&self) returns true.
Converts self into a Right variant of Either<Self, Self>
otherwise. Read more