sv_parser_syntaxtree/source_text/
module_parameters_and_ports.rs

1use crate::*;
2
3// -----------------------------------------------------------------------------
4
5#[derive(Clone, Debug, PartialEq, Node)]
6pub enum ParameterPortList {
7    Assignment(Box<ParameterPortListAssignment>),
8    Declaration(Box<ParameterPortListDeclaration>),
9    Empty(Box<(Symbol, Symbol, Symbol)>),
10}
11
12#[derive(Clone, Debug, PartialEq, Node)]
13pub struct ParameterPortListAssignment {
14    pub nodes: (
15        Symbol,
16        Paren<(
17            ListOfParamAssignments,
18            Vec<(Symbol, ParameterPortDeclaration)>,
19        )>,
20    ),
21}
22
23#[derive(Clone, Debug, PartialEq, Node)]
24pub struct ParameterPortListDeclaration {
25    pub nodes: (Symbol, Paren<List<Symbol, ParameterPortDeclaration>>),
26}
27
28#[derive(Clone, Debug, PartialEq, Node)]
29pub enum ParameterPortDeclaration {
30    ParameterDeclaration(Box<ParameterDeclaration>),
31    LocalParameterDeclaration(Box<LocalParameterDeclaration>),
32    ParamList(Box<ParameterPortDeclarationParamList>),
33    TypeList(Box<ParameterPortDeclarationTypeList>),
34}
35
36#[derive(Clone, Debug, PartialEq, Node)]
37pub struct ParameterPortDeclarationParamList {
38    pub nodes: (DataType, ListOfParamAssignments),
39}
40
41#[derive(Clone, Debug, PartialEq, Node)]
42pub struct ParameterPortDeclarationTypeList {
43    pub nodes: (Keyword, ListOfTypeAssignments),
44}
45
46#[derive(Clone, Debug, PartialEq, Node)]
47pub struct ListOfPorts {
48    pub nodes: (Paren<List<Symbol, Port>>,),
49}
50
51#[derive(Clone, Debug, PartialEq, Node)]
52pub struct ListOfPortDeclarations {
53    pub nodes: (Paren<Option<List<Symbol, (Vec<AttributeInstance>, AnsiPortDeclaration)>>>,),
54}
55
56#[derive(Clone, Debug, PartialEq, Node)]
57pub enum PortDeclaration {
58    Inout(Box<PortDeclarationInout>),
59    Input(Box<PortDeclarationInput>),
60    Output(Box<PortDeclarationOutput>),
61    Ref(Box<PortDeclarationRef>),
62    Interface(Box<PortDeclarationInterface>),
63}
64
65#[derive(Clone, Debug, PartialEq, Node)]
66pub struct PortDeclarationInout {
67    pub nodes: (Vec<AttributeInstance>, InoutDeclaration),
68}
69
70#[derive(Clone, Debug, PartialEq, Node)]
71pub struct PortDeclarationInput {
72    pub nodes: (Vec<AttributeInstance>, InputDeclaration),
73}
74
75#[derive(Clone, Debug, PartialEq, Node)]
76pub struct PortDeclarationOutput {
77    pub nodes: (Vec<AttributeInstance>, OutputDeclaration),
78}
79
80#[derive(Clone, Debug, PartialEq, Node)]
81pub struct PortDeclarationRef {
82    pub nodes: (Vec<AttributeInstance>, RefDeclaration),
83}
84
85#[derive(Clone, Debug, PartialEq, Node)]
86pub struct PortDeclarationInterface {
87    pub nodes: (Vec<AttributeInstance>, InterfacePortDeclaration),
88}
89
90#[derive(Clone, Debug, PartialEq, Node)]
91pub enum Port {
92    NonNamed(Box<PortNonNamed>),
93    Named(Box<PortNamed>),
94}
95
96#[derive(Clone, Debug, PartialEq, Node)]
97pub struct PortNonNamed {
98    pub nodes: (Option<PortExpression>,),
99}
100
101#[derive(Clone, Debug, PartialEq, Node)]
102pub struct PortNamed {
103    pub nodes: (Symbol, PortIdentifier, Paren<Option<PortExpression>>),
104}
105
106#[derive(Clone, Debug, PartialEq, Node)]
107pub enum PortExpression {
108    PortReference(Box<PortReference>),
109    Brace(Box<PortExpressionBrace>),
110}
111
112#[derive(Clone, Debug, PartialEq, Node)]
113pub struct PortExpressionBrace {
114    pub nodes: (Brace<List<Symbol, PortReference>>,),
115}
116
117#[derive(Clone, Debug, PartialEq, Node)]
118pub struct PortReference {
119    pub nodes: (PortIdentifier, ConstantSelect),
120}
121
122#[derive(Clone, Debug, PartialEq, Node)]
123pub enum PortDirection {
124    Input(Box<Keyword>),
125    Output(Box<Keyword>),
126    Inout(Box<Keyword>),
127    Ref(Box<Keyword>),
128}
129
130#[derive(Clone, Debug, PartialEq, Node)]
131pub struct NetPortHeader {
132    pub nodes: (Option<PortDirection>, NetPortType),
133}
134
135#[derive(Clone, Debug, PartialEq, Node)]
136pub struct VariablePortHeader {
137    pub nodes: (Option<PortDirection>, VariablePortType),
138}
139
140#[derive(Clone, Debug, PartialEq, Node)]
141pub enum InterfacePortHeader {
142    Identifier(Box<InterfacePortHeaderIdentifier>),
143    Interface(Box<InterfacePortHeaderInterface>),
144}
145
146#[derive(Clone, Debug, PartialEq, Node)]
147pub struct InterfacePortHeaderIdentifier {
148    pub nodes: (InterfaceIdentifier, Option<(Symbol, ModportIdentifier)>),
149}
150
151#[derive(Clone, Debug, PartialEq, Node)]
152pub struct InterfacePortHeaderInterface {
153    pub nodes: (Keyword, Option<(Symbol, ModportIdentifier)>),
154}
155
156#[derive(Clone, Debug, PartialEq, Node)]
157pub enum NetPortHeaderOrInterfacePortHeader {
158    NetPortHeader(Box<NetPortHeader>),
159    InterfacePortHeader(Box<InterfacePortHeader>),
160}
161#[derive(Clone, Debug, PartialEq, Node)]
162pub enum AnsiPortDeclaration {
163    Net(Box<AnsiPortDeclarationNet>),
164    Variable(Box<AnsiPortDeclarationVariable>),
165    Paren(Box<AnsiPortDeclarationParen>),
166}
167
168#[derive(Clone, Debug, PartialEq, Node)]
169pub struct AnsiPortDeclarationNet {
170    pub nodes: (
171        Option<NetPortHeaderOrInterfacePortHeader>,
172        PortIdentifier,
173        Vec<UnpackedDimension>,
174        Option<(Symbol, ConstantExpression)>,
175    ),
176}
177
178#[derive(Clone, Debug, PartialEq, Node)]
179pub struct AnsiPortDeclarationVariable {
180    pub nodes: (
181        Option<VariablePortHeader>,
182        PortIdentifier,
183        Vec<VariableDimension>,
184        Option<(Symbol, ConstantExpression)>,
185    ),
186}
187
188#[derive(Clone, Debug, PartialEq, Node)]
189pub struct AnsiPortDeclarationParen {
190    pub nodes: (
191        Option<PortDirection>,
192        Symbol,
193        PortIdentifier,
194        Paren<Option<Expression>>,
195    ),
196}
sv_parser_syntaxtree/source_text/module_parameters_and_ports.rs

sv_parser_syntaxtree/source_text/
module_parameters_and_ports.rs
