sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017.
Tools using sv-parser
- morty: A SystemVerilog source file pickler
- svinst: Determines the modules declared and instantiated in a SystemVerilog file
- svlint: SystemVerilog linter
- svls: SystemVerilog language server
Usage
[]
= "0.13.3"
sv-parser provides parse_sv
function which returns SyntaxTree
.
SyntaxTree
shows Concrete Syntax Tree. It has the preprocessed string and the parsed tree.
RefNode
shows a reference to any node of SyntaxTree
.
You can get RefNode
through an iterator of SyntaxTree
.
Variant names of RefNode
follows "Annex A Formal syntax" of IEEE 1800-2017.
Locate
shows a position of token. All leaf node of SyntaxTree
is Locate
.
You can get string from Locate
by get_str
.
Example
The following example parses a SystemVerilog source file and shows module names.
use HashMap;
use env;
use PathBuf;
use ;
License
Licensed under either of
- Apache License, Version 2.0, (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.