Struct sv_parser_syntaxtree::source_text::system_verilog_source_text::ModuleDeclarationAnsi
source · [−]pub struct ModuleDeclarationAnsi {
pub nodes: (ModuleAnsiHeader, Option<TimeunitsDeclaration>, Vec<NonPortModuleItem>, Keyword, Option<(Symbol, ModuleIdentifier)>),
}Fields
nodes: (ModuleAnsiHeader, Option<TimeunitsDeclaration>, Vec<NonPortModuleItem>, Keyword, Option<(Symbol, ModuleIdentifier)>)Trait Implementations
Performs the conversion.
Performs the conversion.
Performs the conversion.
This method tests for self and other values to be equal, and is used
by ==. Read more
This method tests for !=.
Auto Trait Implementations
impl RefUnwindSafe for ModuleDeclarationAnsi
impl Send for ModuleDeclarationAnsi
impl Sync for ModuleDeclarationAnsi
impl Unpin for ModuleDeclarationAnsi
impl UnwindSafe for ModuleDeclarationAnsi
Blanket Implementations
Mutably borrows from an owned value. Read more