Struct Flowgate 

pub struct Flowgate {

    pub name: String,
    pub monitored: Vec<WeightedBranchRef>,
    pub contingency_branch: Option<BranchRef>,
    pub limit_mw: f64,
    pub limit_reverse_mw: f64,
    pub in_service: bool,
    pub limit_mw_schedule: Vec<f64>,
    pub limit_reverse_mw_schedule: Vec<f64>,
    pub hvdc_coefficients: Vec<(usize, f64)>,
    pub ptdf_per_bus: Vec<(u32, f64)>,
    pub hvdc_band_coefficients: Vec<(usize, usize, f64)>,
    pub limit_mw_active_period: Option<u32>,
    pub breach_sides: FlowgateBreachSides,
}

A flowgate: a monitored element under a specific contingency.

Fields

name: String

Human-readable name (e.g. “FG_123”).

monitored: Vec<WeightedBranchRef>

The monitored element(s) with signed coefficients.

contingency_branch: Option<BranchRef>

The contingency element (branch that trips). None = base-case-only flowgate.

limit_mw: f64

Forward MW limit (positive direction defined by monitored_coefficients).

limit_reverse_mw: f64

Reverse MW limit (magnitude of allowable reverse flow). When zero (default), the forward limit is applied symmetrically.

in_service: bool

Whether this flowgate is actively monitored.

limit_mw_schedule: Vec<f64>

Per-timestep forward MW limit schedule (optional).

When non-empty, effective_limit_mw(t) returns schedule[t] for timesteps within range, falling back to limit_mw otherwise. Enables dynamic flowgate limits (ambient ratings, planned outage windows).

limit_reverse_mw_schedule: Vec<f64>

Per-timestep reverse MW limit schedule (optional).

When non-empty, effective_limit_reverse_mw(t) returns schedule[t] for timesteps within range, falling back to limit_reverse_mw otherwise.

hvdc_coefficients: Vec<(usize, f64)>

HVDC link coefficients for N-1 HVDC contingency constraints. Each entry: (hvdc_link_index, coefficient_pu). When non-empty, the flowgate constraint includes HVDC dispatch variable terms: Σ coeff_i·b_dc_i·(θ_from_i − θ_to_i) + Σ hvdc_coeff_k·P_hvdc[k] ∈ [-limit, limit]

ptdf_per_bus: Vec<(u32, f64)>

Per-bus effective PTDF coefficients for the monitored aggregate.

When non-empty, the LP row builder switches from the theta-form constraint Σ coeff·b_dc·Δθ ≤ limit to the PTDF/injection form Σ_i ptdf_eff_i · p_net_inj_i ≤ limit. The latter directly constrains generator/load/storage/HVDC variables and is the only form that binds dispatch when the SCUC LP runs in scuc_disable_bus_power_balance mode (where theta is decoupled from pg). Each entry is (bus_number, eff_ptdf_pu) where eff_ptdf_pu = Σ_term coefficient_term · ptdf_l_term[bus_idx], summed over the flowgate’s monitored terms. Only buses with non-trivial PTDF contribution are stored.

hvdc_band_coefficients: Vec<(usize, usize, f64)>

Per-band HVDC coefficients for banded N-1 HVDC contingency constraints. Each entry: (hvdc_link_index, band_index, coefficient_pu).

limit_mw_active_period: Option<u32>

Compact single-active-period marker. When Some(p), Flowgate::effective_limit_mw returns limit_mw at timestep p and the INACTIVE_FLOWGATE_LIMIT_MW sentinel for all other timesteps — producing the same LP behaviour as a 18-slot limit_mw_schedule with 17 sentinel entries but without the per-flowgate Vec<f64> allocation (~1.2 GB savings on 617-bus explicit N-1 SCUC, where this is populated by build_branch_security_flowgate). When None, the legacy limit_mw_schedule / limit_mw lookup is used unchanged.

breach_sides: FlowgateBreachSides

Which side(s) of the flowgate limit can bind. Defaults to FlowgateBreachSides::Both for user-supplied or preseeded cuts where the screener doesn’t know the direction. The iterative security-SCUC screener emits FlowgateBreachSides::Upper or FlowgateBreachSides::Lower after observing which side of ±limit_mw the monitored-branch flow actually crossed, so the bounds layer can pin the non-breached side’s slack column to zero and let the surge lp-reduce presolve drop it. Saves a factor-of-two on slack columns per (flowgate, period) pair when set.

Implementations

impl Flowgate

pub fn effective_limit_mw(&self, t: usize) -> f64

Forward MW limit at timestep t.

Resolution order:

1. If limit_mw_active_period is Some(p): return limit_mw at t == p, and INACTIVE_FLOWGATE_LIMIT_MW otherwise. This is the compact encoding used by explicit N-1 security flowgates (one period active, all others disabled). Avoids allocating an n_periods-length Vec<f64> per flowgate.
2. Else if limit_mw_schedule[t] exists: return it.
3. Else: fall back to limit_mw.

pub fn effective_limit_reverse_mw(&self, t: usize) -> f64

Reverse MW limit at timestep t.

Returns limit_reverse_mw_schedule[t] when available, else limit_reverse_mw. When the result is zero (or negative), callers should fall back to the forward limit for symmetric enforcement.

pub fn effective_reverse_or_forward(&self, t: usize) -> f64

Effective reverse limit, falling back to forward limit when zero.

This is the convenience method for constraint generation: returns the reverse limit if explicitly set (> 0), otherwise the forward limit for symmetric enforcement.

Trait Implementations

impl Clone for Flowgate

fn clone(&self) -> Flowgate

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Flowgate

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'de> Deserialize<'de> for Flowgate

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Serialize for Flowgate

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.