#[repr(u8)]pub enum GfBackend {
Scalar = 0,
Ssse3 = 1,
Avx2 = 2,
Avx512Pshufb = 3,
Gfni256 = 4,
Gfni512 = 5,
AffineScalar = 6,
Neon = 7,
}Expand description
GF(256) multiply-add backend, exposed so an A/B bench can compare every
SIMD rung against the scalar baseline and so the GFNI / AVX-512 logic can be
validated on a host without the silicon via the bit-exact software affine
emulation. The production hot loop (gf_mul_add) auto-selects the fastest
rung this host can run; the ladder always bottoms out at Scalar.
Variants§
Scalar = 0
Portable table-lookup multiply. Always available; the fallback floor.
Ssse3 = 1
SSSE3 PSHUFB nibble-table multiply, 16 bytes per op.
Avx2 = 2
AVX2 PSHUFB nibble-table multiply, 32 bytes per op.
Avx512Pshufb = 3
AVX-512BW PSHUFB nibble-table multiply, 64 bytes per op (no GFNI).
Gfni256 = 4
GFNI affine GF(2^8) multiply on 256-bit lanes: a hardware field multiply
(no table), broad consumer reach (gfni + avx2, no AVX-512 needed).
Gfni512 = 5
GFNI affine GF(2^8) multiply on 512-bit lanes: 64 bytes per op in one hardware instruction.
AffineScalar = 6
Software emulation of the GFNI affine transform: bit-exact to the GFNI hardware path, runnable on any host. Validates the GFNI logic where the silicon is absent, the same emulate-to-verify approach the AVX-512 substrate uses.
Neon = 7
ARM NEON TBL nibble-table multiply, 16 bytes per vqtbl1q_u8. The
aarch64 byte-shuffle rung: the same nibble-table technique as SSSE3, so
bit-identical to it (and to scalar). NEON is baseline on every aarch64
CPU, so this rung is always available on Apple Silicon / Neoverse.