pub trait Exti {
const INTERRUPT: Interrupt;
// Required methods
fn set_port(syscfg: &mut SYSCFG);
fn set_rising_trigger(exti: &mut EXTI, en: bool);
fn set_falling_trigger(exti: &mut EXTI, en: bool);
fn set_c1_mask(exti: &mut EXTI, unmask: bool);
fn clear_exti();
fn is_pending() -> bool;
// Provided methods
fn setup_exti_c1(exti: &mut EXTI, syscfg: &mut SYSCFG, trg: ExtiTrg) { ... }
unsafe fn unmask() { ... }
fn mask() { ... }
}Expand description
Input pin extended interrupts.
Required Associated Constants§
Required Methods§
Sourcefn set_port(syscfg: &mut SYSCFG)
fn set_port(syscfg: &mut SYSCFG)
Set the current port as the interrupt source.
Only one port (A, B, C) can be active at a time for each pin number. For example, enabling PA2 will disable PB2 and PC2 if previously enabled.
§Example
Set port C as the pin-6 EXTI port.
use stm32wlxx_hal::{
gpio::{pins::C6, Exti},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::set_port(&mut dp.SYSCFG);Sourcefn set_rising_trigger(exti: &mut EXTI, en: bool)
fn set_rising_trigger(exti: &mut EXTI, en: bool)
Set the rising trigger enable.
§Example
Set C6 to trigger on a rising edge.
use stm32wlxx_hal::{
gpio::{pins::C6, Exti},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::set_port(&mut dp.SYSCFG);
C6::set_rising_trigger(&mut dp.EXTI, true);Sourcefn set_falling_trigger(exti: &mut EXTI, en: bool)
fn set_falling_trigger(exti: &mut EXTI, en: bool)
Set the falling trigger enable.
§Example
Set C6 to trigger on a falling edge.
use stm32wlxx_hal::{
gpio::{pins::C6, Exti},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::set_port(&mut dp.SYSCFG);
C6::set_falling_trigger(&mut dp.EXTI, true);Sourcefn set_c1_mask(exti: &mut EXTI, unmask: bool)
fn set_c1_mask(exti: &mut EXTI, unmask: bool)
Set the core 1 interrupt mask in the EXTI.
This will not mask/unmask the IRQ in the NVIC, use
mask and unmask for that.
§Example
Unmask C6.
use stm32wlxx_hal::{
gpio::{pins::C6, Exti},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::set_port(&mut dp.SYSCFG);
C6::set_c1_mask(&mut dp.EXTI, true);Sourcefn clear_exti()
fn clear_exti()
Sourcefn is_pending() -> bool
fn is_pending() -> bool
Provided Methods§
Sourcefn setup_exti_c1(exti: &mut EXTI, syscfg: &mut SYSCFG, trg: ExtiTrg)
fn setup_exti_c1(exti: &mut EXTI, syscfg: &mut SYSCFG, trg: ExtiTrg)
Setup an input pin as an EXTI interrupt source on core 1.
This is a helper function that wraps:
set_portset_rising_triggerset_falling_trigger- Unmask with
set_c1_mask
§Example
Setup C6 to trigger on both edges.
use stm32wlxx_hal::{
gpio::{pins::C6, Exti, ExtiTrg},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::setup_exti_c1(&mut dp.EXTI, &mut dp.SYSCFG, ExtiTrg::Both);Sourceunsafe fn unmask()
unsafe fn unmask()
Unmask the interrupt in the NVIC.
This will not unmask the IRQ in the EXTI,
use set_c1_mask for that.
§Safety
This can break mask-based critical sections.
§Example
Setup and unmask C6 (which will unmask all pins 5-9).
use stm32wlxx_hal::{
gpio::{pins::C6, Exti, ExtiTrg},
pac,
};
let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
C6::setup_exti_c1(&mut dp.EXTI, &mut dp.SYSCFG, ExtiTrg::Both);
unsafe { C6::unmask() };Sourcefn mask()
fn mask()
Mask the interrupt in the NVIC.
This will not mask the IRQ in the EXTI,
use set_c1_mask for that.
§Example
Mask C6 (which will mask all pins 5-9).
use stm32wlxx_hal::gpio::{pins::C6, Exti};
C6::mask();Dyn Compatibility§
This trait is not dyn compatible.
In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.