Struct R

pub struct R<U, T> { /* private fields */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Implementations

impl<U, T> R<U, T>

where U: Copy,

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u32, Reg<u32, _ISR>>

pub fn teif7(&self) -> TEIF7_R

Bit 27 - Channel x transfer error flag (x = 1 ..7)

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif7(&self) -> TCIF7_R

Bit 25 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif7(&self) -> GIF7_R

Bit 24 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif6(&self) -> TEIF6_R

Bit 23 - Channel x transfer error flag (x = 1 ..7)

pub fn htif6(&self) -> HTIF6_R

Bit 22 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif6(&self) -> GIF6_R

Bit 20 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel x transfer error flag (x = 1 ..7)

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel x transfer error flag (x = 1 ..7)

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel x transfer error flag (x = 1 ..7)

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel x transfer error flag (x = 1 ..7)

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel x transfer error flag (x = 1 ..7)

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel x global interrupt flag (x = 1 ..7)

impl R<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR1>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR1>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR2>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR2>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR3>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR3>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR4>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR4>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR5>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR5>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR6>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR6>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR7>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR7>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _ISR>>

pub fn teif7(&self) -> TEIF7_R

Bit 27 - Channel x transfer error flag (x = 1 ..7)

pub fn htif7(&self) -> HTIF7_R

Bit 26 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif7(&self) -> TCIF7_R

Bit 25 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif7(&self) -> GIF7_R

Bit 24 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif6(&self) -> TEIF6_R

Bit 23 - Channel x transfer error flag (x = 1 ..7)

pub fn htif6(&self) -> HTIF6_R

Bit 22 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif6(&self) -> TCIF6_R

Bit 21 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif6(&self) -> GIF6_R

Bit 20 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif5(&self) -> TEIF5_R

Bit 19 - Channel x transfer error flag (x = 1 ..7)

pub fn htif5(&self) -> HTIF5_R

Bit 18 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif5(&self) -> TCIF5_R

Bit 17 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif5(&self) -> GIF5_R

Bit 16 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif4(&self) -> TEIF4_R

Bit 15 - Channel x transfer error flag (x = 1 ..7)

pub fn htif4(&self) -> HTIF4_R

Bit 14 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif4(&self) -> TCIF4_R

Bit 13 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif4(&self) -> GIF4_R

Bit 12 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif3(&self) -> TEIF3_R

Bit 11 - Channel x transfer error flag (x = 1 ..7)

pub fn htif3(&self) -> HTIF3_R

Bit 10 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif3(&self) -> TCIF3_R

Bit 9 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif3(&self) -> GIF3_R

Bit 8 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif2(&self) -> TEIF2_R

Bit 7 - Channel x transfer error flag (x = 1 ..7)

pub fn htif2(&self) -> HTIF2_R

Bit 6 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif2(&self) -> TCIF2_R

Bit 5 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif2(&self) -> GIF2_R

Bit 4 - Channel x global interrupt flag (x = 1 ..7)

pub fn teif1(&self) -> TEIF1_R

Bit 3 - Channel x transfer error flag (x = 1 ..7)

pub fn htif1(&self) -> HTIF1_R

Bit 2 - Channel x half transfer flag (x = 1 ..7)

pub fn tcif1(&self) -> TCIF1_R

Bit 1 - Channel x transfer complete flag (x = 1 ..7)

pub fn gif1(&self) -> GIF1_R

Bit 0 - Channel x global interrupt flag (x = 1 ..7)

impl R<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR1>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR1>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR2>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR2>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR3>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR3>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR4>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR4>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR5>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR5>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR6>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR6>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&self) -> MEM2MEM_R

Bit 14 - Memory to memory mode

pub fn pl(&self) -> PL_R

Bits 12:13 - Channel priority level

pub fn msize(&self) -> MSIZE_R

Bits 10:11 - Memory size

pub fn psize(&self) -> PSIZE_R

Bits 8:9 - Peripheral size

pub fn minc(&self) -> MINC_R

Bit 7 - Memory increment mode

pub fn pinc(&self) -> PINC_R

Bit 6 - Peripheral increment mode

pub fn circ(&self) -> CIRC_R

Bit 5 - Circular mode

pub fn dir(&self) -> DIR_R

Bit 4 - Data transfer direction

pub fn teie(&self) -> TEIE_R

Bit 3 - Transfer error interrupt enable

pub fn htie(&self) -> HTIE_R

Bit 2 - Half transfer interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 1 - Transfer complete interrupt enable

pub fn en(&self) -> EN_R

Bit 0 - Channel enable

impl R<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&self) -> NDT_R

Bits 0:15 - Number of data to transfer

impl R<u32, Reg<u32, _CPAR7>>

pub fn pa(&self) -> PA_R

Bits 0:31 - Peripheral address

impl R<u32, Reg<u32, _CMAR7>>

pub fn ma(&self) -> MA_R

Bits 0:31 - Memory address

impl R<u32, Reg<u32, _CSELR>>

pub fn c7s(&self) -> C7S_R

Bits 24:27 - DMA channel 7 selection

pub fn c6s(&self) -> C6S_R

Bits 20:23 - DMA channel 6 selection

pub fn c5s(&self) -> C5S_R

Bits 16:19 - DMA channel 5 selection

pub fn c4s(&self) -> C4S_R

Bits 12:15 - DMA channel 4 selection

pub fn c3s(&self) -> C3S_R

Bits 8:11 - DMA channel 3 selection

pub fn c2s(&self) -> C2S_R

Bits 4:7 - DMA channel 2 selection

pub fn c1s(&self) -> C1S_R

Bits 0:3 - DMA channel 1 selection

impl R<u32, Reg<u32, _C0CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C1CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C2CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C3CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C4CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C5CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C6CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C7CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C8CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C9CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C10CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C11CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C12CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _C13CR>>

pub fn sync_id(&self) -> SYNC_ID_R

Bits 24:28 - SYNC_ID

pub fn nbreq(&self) -> NBREQ_R

Bits 19:23 - Nb request

pub fn spol(&self) -> SPOL_R

Bits 17:18 - Sync polarity

pub fn se(&self) -> SE_R

Bit 16 - Synchronization enable

pub fn ege(&self) -> EGE_R

Bit 9 - Event Generation Enable

pub fn soie(&self) -> SOIE_R

Bit 8 - Synchronization Overrun Interrupt Enable

pub fn dmareq_id(&self) -> DMAREQ_ID_R

Bits 0:7 - DMA Request ID

impl R<u32, Reg<u32, _CSR>>

pub fn sof0(&self) -> SOF0_R

Bit 0 - Synchronization Overrun Flag 0

pub fn sof1(&self) -> SOF1_R

Bit 1 - Synchronization Overrun Flag 1

pub fn sof2(&self) -> SOF2_R

Bit 2 - Synchronization Overrun Flag 2

pub fn sof3(&self) -> SOF3_R

Bit 3 - Synchronization Overrun Flag 3

pub fn sof4(&self) -> SOF4_R

Bit 4 - Synchronization Overrun Flag 4

pub fn sof5(&self) -> SOF5_R

Bit 5 - Synchronization Overrun Flag 5

pub fn sof6(&self) -> SOF6_R

Bit 6 - Synchronization Overrun Flag 6

pub fn sof7(&self) -> SOF7_R

Bit 7 - Synchronization Overrun Flag 7

pub fn sof8(&self) -> SOF8_R

Bit 8 - Synchronization Overrun Flag 8

pub fn sof9(&self) -> SOF9_R

Bit 9 - Synchronization Overrun Flag 9

pub fn sof10(&self) -> SOF10_R

Bit 10 - Synchronization Overrun Flag 10

pub fn sof11(&self) -> SOF11_R

Bit 11 - Synchronization Overrun Flag 11

pub fn sof12(&self) -> SOF12_R

Bit 12 - Synchronization Overrun Flag 12

pub fn sof13(&self) -> SOF13_R

Bit 13 - Synchronization Overrun Flag 13

impl R<u32, Reg<u32, _RG0CR>>

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of Request

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - Generation Polarity

pub fn ge(&self) -> GE_R

Bit 16 - Generation Enable

pub fn oie(&self) -> OIE_R

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - Signal ID

impl R<u32, Reg<u32, _RG1CR>>

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of Request

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - Generation Polarity

pub fn ge(&self) -> GE_R

Bit 16 - Generation Enable

pub fn oie(&self) -> OIE_R

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - Signal ID

impl R<u32, Reg<u32, _RG2CR>>

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of Request

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - Generation Polarity

pub fn ge(&self) -> GE_R

Bit 16 - Generation Enable

pub fn oie(&self) -> OIE_R

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - Signal ID

impl R<u32, Reg<u32, _RG3CR>>

pub fn gnbreq(&self) -> GNBREQ_R

Bits 19:23 - Number of Request

pub fn gpol(&self) -> GPOL_R

Bits 17:18 - Generation Polarity

pub fn ge(&self) -> GE_R

Bit 16 - Generation Enable

pub fn oie(&self) -> OIE_R

Bit 8 - Overrun Interrupt Enable

pub fn sig_id(&self) -> SIG_ID_R

Bits 0:4 - Signal ID

impl R<u32, Reg<u32, _RGSR>>

pub fn of0(&self) -> OF0_R

Bit 0 - Generator Overrun Flag 0

pub fn of1(&self) -> OF1_R

Bit 1 - Generator Overrun Flag 1

pub fn of2(&self) -> OF2_R

Bit 2 - Generator Overrun Flag 2

pub fn of3(&self) -> OF3_R

Bit 3 - Generator Overrun Flag 3

impl R<u32, Reg<u32, _RGCFR>>

pub fn csof0(&self) -> CSOF0_R

Bit 0 - Generator Clear Overrun Flag 0

pub fn csof1(&self) -> CSOF1_R

Bit 1 - Generator Clear Overrun Flag 1

pub fn csof2(&self) -> CSOF2_R

Bit 2 - Generator Clear Overrun Flag 2

pub fn csof3(&self) -> CSOF3_R

Bit 3 - Generator Clear Overrun Flag 3

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:31 - Data register bits

impl R<u32, Reg<u32, _IDR>>

pub fn idr(&self) -> IDR_R

Bits 0:31 - General-purpose 32-bit data register bits

impl R<u32, Reg<u32, _CR>>

pub fn rev_out(&self) -> REV_OUT_R

Bit 7 - Reverse output data

pub fn rev_in(&self) -> REV_IN_R

Bits 5:6 - Reverse input data

pub fn polysize(&self) -> POLYSIZE_R

Bits 3:4 - Polynomial size

pub fn reset(&self) -> RESET_R

Bit 0 - RESET bit

impl R<u32, Reg<u32, _INIT>>

pub fn crc_init(&self) -> CRC_INIT_R

Bits 0:31 - Programmable initial CRC value

impl R<u32, Reg<u32, _POL>>

pub fn pol(&self) -> POL_R

Bits 0:31 - Programmable polynomial

impl R<u32, Reg<u32, _CR>>

pub fn bias(&self) -> BIAS_R

Bits 5:6 - Bias selector

pub fn duty(&self) -> DUTY_R

Bits 2:4 - Duty selection

pub fn vsel(&self) -> VSEL_R

Bit 1 - Voltage source selection

pub fn lcden(&self) -> LCDEN_R

Bit 0 - LCD controller enable

pub fn mux_seg(&self) -> MUX_SEG_R

Bit 7 - Mux segment enable

pub fn bufen(&self) -> BUFEN_R

Bit 8 - Voltage output buffer enable

impl R<u32, Reg<u32, _FCR>>

pub fn ps(&self) -> PS_R

Bits 22:25 - PS 16-bit prescaler

pub fn div(&self) -> DIV_R

Bits 18:21 - DIV clock divider

pub fn blink(&self) -> BLINK_R

Bits 16:17 - Blink mode selection

pub fn blinkf(&self) -> BLINKF_R

Bits 13:15 - Blink frequency selection

pub fn cc(&self) -> CC_R

Bits 10:12 - Contrast control

pub fn dead(&self) -> DEAD_R

Bits 7:9 - Dead time duration

pub fn pon(&self) -> PON_R

Bits 4:6 - Pulse ON duration

pub fn uddie(&self) -> UDDIE_R

Bit 3 - Update display done interrupt enable

pub fn sofie(&self) -> SOFIE_R

Bit 1 - Start of frame interrupt enable

pub fn hd(&self) -> HD_R

Bit 0 - High drive enable

impl R<u32, Reg<u32, _SR>>

pub fn fcrsf(&self) -> FCRSF_R

Bit 5 - LCD Frame Control Register Synchronization flag

pub fn rdy(&self) -> RDY_R

Bit 4 - Ready flag

pub fn udd(&self) -> UDD_R

Bit 3 - Update Display Done

pub fn udr(&self) -> UDR_R

Bit 2 - Update display request

pub fn sof(&self) -> SOF_R

Bit 1 - Start of frame flag

pub fn ens(&self) -> ENS_R

Bit 0 - ENS

impl R<u32, Reg<u32, _RAM_COM0>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM1>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM2>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM3>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM4>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM5>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM6>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _RAM_COM7>>

pub fn s31(&self) -> S31_R

Bit 31 - S31

pub fn s30(&self) -> S30_R

Bit 30 - S30

pub fn s29(&self) -> S29_R

Bit 29 - S29

pub fn s28(&self) -> S28_R

Bit 28 - S28

pub fn s27(&self) -> S27_R

Bit 27 - S27

pub fn s26(&self) -> S26_R

Bit 26 - S26

pub fn s25(&self) -> S25_R

Bit 25 - S25

pub fn s24(&self) -> S24_R

Bit 24 - S24

pub fn s23(&self) -> S23_R

Bit 23 - S23

pub fn s22(&self) -> S22_R

Bit 22 - S22

pub fn s21(&self) -> S21_R

Bit 21 - S21

pub fn s20(&self) -> S20_R

Bit 20 - S20

pub fn s19(&self) -> S19_R

Bit 19 - S19

pub fn s18(&self) -> S18_R

Bit 18 - S18

pub fn s17(&self) -> S17_R

Bit 17 - S17

pub fn s16(&self) -> S16_R

Bit 16 - S16

pub fn s15(&self) -> S15_R

Bit 15 - S15

pub fn s14(&self) -> S14_R

Bit 14 - S14

pub fn s13(&self) -> S13_R

Bit 13 - S13

pub fn s12(&self) -> S12_R

Bit 12 - S12

pub fn s11(&self) -> S11_R

Bit 11 - S11

pub fn s10(&self) -> S10_R

Bit 10 - S10

pub fn s09(&self) -> S09_R

Bit 9 - S09

pub fn s08(&self) -> S08_R

Bit 8 - S08

pub fn s07(&self) -> S07_R

Bit 7 - S07

pub fn s06(&self) -> S06_R

Bit 6 - S06

pub fn s05(&self) -> S05_R

Bit 5 - S05

pub fn s04(&self) -> S04_R

Bit 4 - S04

pub fn s03(&self) -> S03_R

Bit 3 - S03

pub fn s02(&self) -> S02_R

Bit 2 - S02

pub fn s01(&self) -> S01_R

Bit 1 - S01

pub fn s00(&self) -> S00_R

Bit 0 - S00

impl R<u32, Reg<u32, _CR>>

pub fn ctph(&self) -> CTPH_R

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&self) -> CTPL_R

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&self) -> SSD_R

Bits 17:23 - Spread spectrum deviation

pub fn sse(&self) -> SSE_R

Bit 16 - Spread spectrum enable

pub fn sspsc(&self) -> SSPSC_R

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&self) -> PGPSC_R

Bits 12:14 - pulse generator prescaler

pub fn mcv(&self) -> MCV_R

Bits 5:7 - Max count value

pub fn iodef(&self) -> IODEF_R

Bit 4 - I/O Default mode

pub fn syncpol(&self) -> SYNCPOL_R

Bit 3 - Synchronization pin polarity

pub fn am(&self) -> AM_R

Bit 2 - Acquisition mode

pub fn start(&self) -> START_R

Bit 1 - Start a new acquisition

pub fn tsce(&self) -> TSCE_R

Bit 0 - Touch sensing controller enable

impl R<u32, Reg<u32, _IER>>

pub fn mceie(&self) -> MCEIE_R

Bit 1 - Max count error interrupt enable

pub fn eoaie(&self) -> EOAIE_R

Bit 0 - End of acquisition interrupt enable

impl R<u32, Reg<u32, _ICR>>

pub fn mceic(&self) -> MCEIC_R

Bit 1 - Max count error interrupt clear

pub fn eoaic(&self) -> EOAIC_R

Bit 0 - End of acquisition interrupt clear

impl R<u32, Reg<u32, _ISR>>

pub fn mcef(&self) -> MCEF_R

Bit 1 - Max count error flag

pub fn eoaf(&self) -> EOAF_R

Bit 0 - End of acquisition flag

impl R<u32, Reg<u32, _IOHCR>>

pub fn g7_io4(&self) -> G7_IO4_R

Bit 27 - G7_IO4

pub fn g7_io3(&self) -> G7_IO3_R

Bit 26 - G7_IO3

pub fn g7_io2(&self) -> G7_IO2_R

Bit 25 - G7_IO2

pub fn g7_io1(&self) -> G7_IO1_R

Bit 24 - G7_IO1

pub fn g6_io4(&self) -> G6_IO4_R

Bit 23 - G6_IO4

pub fn g6_io3(&self) -> G6_IO3_R

Bit 22 - G6_IO3

pub fn g6_io2(&self) -> G6_IO2_R

Bit 21 - G6_IO2

pub fn g6_io1(&self) -> G6_IO1_R

Bit 20 - G6_IO1

pub fn g5_io4(&self) -> G5_IO4_R

Bit 19 - G5_IO4

pub fn g5_io3(&self) -> G5_IO3_R

Bit 18 - G5_IO3

pub fn g5_io2(&self) -> G5_IO2_R

Bit 17 - G5_IO2

pub fn g5_io1(&self) -> G5_IO1_R

Bit 16 - G5_IO1

pub fn g4_io4(&self) -> G4_IO4_R

Bit 15 - G4_IO4

pub fn g4_io3(&self) -> G4_IO3_R

Bit 14 - G4_IO3

pub fn g4_io2(&self) -> G4_IO2_R

Bit 13 - G4_IO2

pub fn g4_io1(&self) -> G4_IO1_R

Bit 12 - G4_IO1

pub fn g3_io4(&self) -> G3_IO4_R

Bit 11 - G3_IO4

pub fn g3_io3(&self) -> G3_IO3_R

Bit 10 - G3_IO3

pub fn g3_io2(&self) -> G3_IO2_R

Bit 9 - G3_IO2

pub fn g3_io1(&self) -> G3_IO1_R

Bit 8 - G3_IO1

pub fn g2_io4(&self) -> G2_IO4_R

Bit 7 - G2_IO4

pub fn g2_io3(&self) -> G2_IO3_R

Bit 6 - G2_IO3

pub fn g2_io2(&self) -> G2_IO2_R

Bit 5 - G2_IO2

pub fn g2_io1(&self) -> G2_IO1_R

Bit 4 - G2_IO1

pub fn g1_io4(&self) -> G1_IO4_R

Bit 3 - G1_IO4

pub fn g1_io3(&self) -> G1_IO3_R

Bit 2 - G1_IO3

pub fn g1_io2(&self) -> G1_IO2_R

Bit 1 - G1_IO2

pub fn g1_io1(&self) -> G1_IO1_R

Bit 0 - G1_IO1

impl R<u32, Reg<u32, _IOASCR>>

pub fn g7_io4(&self) -> G7_IO4_R

Bit 27 - G7_IO4

pub fn g7_io3(&self) -> G7_IO3_R

Bit 26 - G7_IO3

pub fn g7_io2(&self) -> G7_IO2_R

Bit 25 - G7_IO2

pub fn g7_io1(&self) -> G7_IO1_R

Bit 24 - G7_IO1

pub fn g6_io4(&self) -> G6_IO4_R

Bit 23 - G6_IO4

pub fn g6_io3(&self) -> G6_IO3_R

Bit 22 - G6_IO3

pub fn g6_io2(&self) -> G6_IO2_R

Bit 21 - G6_IO2

pub fn g6_io1(&self) -> G6_IO1_R

Bit 20 - G6_IO1

pub fn g5_io4(&self) -> G5_IO4_R

Bit 19 - G5_IO4

pub fn g5_io3(&self) -> G5_IO3_R

Bit 18 - G5_IO3

pub fn g5_io2(&self) -> G5_IO2_R

Bit 17 - G5_IO2

pub fn g5_io1(&self) -> G5_IO1_R

Bit 16 - G5_IO1

pub fn g4_io4(&self) -> G4_IO4_R

Bit 15 - G4_IO4

pub fn g4_io3(&self) -> G4_IO3_R

Bit 14 - G4_IO3

pub fn g4_io2(&self) -> G4_IO2_R

Bit 13 - G4_IO2

pub fn g4_io1(&self) -> G4_IO1_R

Bit 12 - G4_IO1

pub fn g3_io4(&self) -> G3_IO4_R

Bit 11 - G3_IO4

pub fn g3_io3(&self) -> G3_IO3_R

Bit 10 - G3_IO3

pub fn g3_io2(&self) -> G3_IO2_R

Bit 9 - G3_IO2

pub fn g3_io1(&self) -> G3_IO1_R

Bit 8 - G3_IO1

pub fn g2_io4(&self) -> G2_IO4_R

Bit 7 - G2_IO4

pub fn g2_io3(&self) -> G2_IO3_R

Bit 6 - G2_IO3

pub fn g2_io2(&self) -> G2_IO2_R

Bit 5 - G2_IO2

pub fn g2_io1(&self) -> G2_IO1_R

Bit 4 - G2_IO1

pub fn g1_io4(&self) -> G1_IO4_R

Bit 3 - G1_IO4

pub fn g1_io3(&self) -> G1_IO3_R

Bit 2 - G1_IO3

pub fn g1_io2(&self) -> G1_IO2_R

Bit 1 - G1_IO2

pub fn g1_io1(&self) -> G1_IO1_R

Bit 0 - G1_IO1

impl R<u32, Reg<u32, _IOSCR>>

pub fn g7_io4(&self) -> G7_IO4_R

Bit 27 - G7_IO4

pub fn g7_io3(&self) -> G7_IO3_R

Bit 26 - G7_IO3

pub fn g7_io2(&self) -> G7_IO2_R

Bit 25 - G7_IO2

pub fn g7_io1(&self) -> G7_IO1_R

Bit 24 - G7_IO1

pub fn g6_io4(&self) -> G6_IO4_R

Bit 23 - G6_IO4

pub fn g6_io3(&self) -> G6_IO3_R

Bit 22 - G6_IO3

pub fn g6_io2(&self) -> G6_IO2_R

Bit 21 - G6_IO2

pub fn g6_io1(&self) -> G6_IO1_R

Bit 20 - G6_IO1

pub fn g5_io4(&self) -> G5_IO4_R

Bit 19 - G5_IO4

pub fn g5_io3(&self) -> G5_IO3_R

Bit 18 - G5_IO3

pub fn g5_io2(&self) -> G5_IO2_R

Bit 17 - G5_IO2

pub fn g5_io1(&self) -> G5_IO1_R

Bit 16 - G5_IO1

pub fn g4_io4(&self) -> G4_IO4_R

Bit 15 - G4_IO4

pub fn g4_io3(&self) -> G4_IO3_R

Bit 14 - G4_IO3

pub fn g4_io2(&self) -> G4_IO2_R

Bit 13 - G4_IO2

pub fn g4_io1(&self) -> G4_IO1_R

Bit 12 - G4_IO1

pub fn g3_io4(&self) -> G3_IO4_R

Bit 11 - G3_IO4

pub fn g3_io3(&self) -> G3_IO3_R

Bit 10 - G3_IO3

pub fn g3_io2(&self) -> G3_IO2_R

Bit 9 - G3_IO2

pub fn g3_io1(&self) -> G3_IO1_R

Bit 8 - G3_IO1

pub fn g2_io4(&self) -> G2_IO4_R

Bit 7 - G2_IO4

pub fn g2_io3(&self) -> G2_IO3_R

Bit 6 - G2_IO3

pub fn g2_io2(&self) -> G2_IO2_R

Bit 5 - G2_IO2

pub fn g2_io1(&self) -> G2_IO1_R

Bit 4 - G2_IO1

pub fn g1_io4(&self) -> G1_IO4_R

Bit 3 - G1_IO4

pub fn g1_io3(&self) -> G1_IO3_R

Bit 2 - G1_IO3

pub fn g1_io2(&self) -> G1_IO2_R

Bit 1 - G1_IO2

pub fn g1_io1(&self) -> G1_IO1_R

Bit 0 - G1_IO1

impl R<u32, Reg<u32, _IOCCR>>

pub fn g7_io4(&self) -> G7_IO4_R

Bit 27 - G7_IO4

pub fn g7_io3(&self) -> G7_IO3_R

Bit 26 - G7_IO3

pub fn g7_io2(&self) -> G7_IO2_R

Bit 25 - G7_IO2

pub fn g7_io1(&self) -> G7_IO1_R

Bit 24 - G7_IO1

pub fn g6_io4(&self) -> G6_IO4_R

Bit 23 - G6_IO4

pub fn g6_io3(&self) -> G6_IO3_R

Bit 22 - G6_IO3

pub fn g6_io2(&self) -> G6_IO2_R

Bit 21 - G6_IO2

pub fn g6_io1(&self) -> G6_IO1_R

Bit 20 - G6_IO1

pub fn g5_io4(&self) -> G5_IO4_R

Bit 19 - G5_IO4

pub fn g5_io3(&self) -> G5_IO3_R

Bit 18 - G5_IO3

pub fn g5_io2(&self) -> G5_IO2_R

Bit 17 - G5_IO2

pub fn g5_io1(&self) -> G5_IO1_R

Bit 16 - G5_IO1

pub fn g4_io4(&self) -> G4_IO4_R

Bit 15 - G4_IO4

pub fn g4_io3(&self) -> G4_IO3_R

Bit 14 - G4_IO3

pub fn g4_io2(&self) -> G4_IO2_R

Bit 13 - G4_IO2

pub fn g4_io1(&self) -> G4_IO1_R

Bit 12 - G4_IO1

pub fn g3_io4(&self) -> G3_IO4_R

Bit 11 - G3_IO4

pub fn g3_io3(&self) -> G3_IO3_R

Bit 10 - G3_IO3

pub fn g3_io2(&self) -> G3_IO2_R

Bit 9 - G3_IO2

pub fn g3_io1(&self) -> G3_IO1_R

Bit 8 - G3_IO1

pub fn g2_io4(&self) -> G2_IO4_R

Bit 7 - G2_IO4

pub fn g2_io3(&self) -> G2_IO3_R

Bit 6 - G2_IO3

pub fn g2_io2(&self) -> G2_IO2_R

Bit 5 - G2_IO2

pub fn g2_io1(&self) -> G2_IO1_R

Bit 4 - G2_IO1

pub fn g1_io4(&self) -> G1_IO4_R

Bit 3 - G1_IO4

pub fn g1_io3(&self) -> G1_IO3_R

Bit 2 - G1_IO3

pub fn g1_io2(&self) -> G1_IO2_R

Bit 1 - G1_IO2

pub fn g1_io1(&self) -> G1_IO1_R

Bit 0 - G1_IO1

impl R<u32, Reg<u32, _IOGCSR>>

pub fn g7s(&self) -> G7S_R

Bit 22 - Analog I/O group x status

pub fn g6s(&self) -> G6S_R

Bit 21 - Analog I/O group x status

pub fn g5s(&self) -> G5S_R

Bit 20 - Analog I/O group x status

pub fn g4s(&self) -> G4S_R

Bit 19 - Analog I/O group x status

pub fn g3s(&self) -> G3S_R

Bit 18 - Analog I/O group x status

pub fn g2s(&self) -> G2S_R

Bit 17 - Analog I/O group x status

pub fn g1s(&self) -> G1S_R

Bit 16 - Analog I/O group x status

pub fn g7e(&self) -> G7E_R

Bit 6 - Analog I/O group x enable

pub fn g6e(&self) -> G6E_R

Bit 5 - Analog I/O group x enable

pub fn g5e(&self) -> G5E_R

Bit 4 - Analog I/O group x enable

pub fn g4e(&self) -> G4E_R

Bit 3 - Analog I/O group x enable

pub fn g3e(&self) -> G3E_R

Bit 2 - Analog I/O group x enable

pub fn g2e(&self) -> G2E_R

Bit 1 - Analog I/O group x enable

pub fn g1e(&self) -> G1E_R

Bit 0 - Analog I/O group x enable

impl R<u32, Reg<u32, _IOG1CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG2CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG3CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG4CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG5CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG6CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _IOG7CR>>

pub fn cnt(&self) -> CNT_R

Bits 0:13 - Counter value

impl R<u32, Reg<u32, _PR>>

pub fn pr(&self) -> PR_R

Bits 0:2 - Prescaler divider

impl R<u32, Reg<u32, _RLR>>

pub fn rl(&self) -> RL_R

Bits 0:11 - Watchdog counter reload value

impl R<u32, Reg<u32, _SR>>

pub fn wvu(&self) -> WVU_R

Bit 2 - Watchdog counter window value update

pub fn rvu(&self) -> RVU_R

Bit 1 - Watchdog counter reload value update

pub fn pvu(&self) -> PVU_R

Bit 0 - Watchdog prescaler value update

impl R<u32, Reg<u32, _WINR>>

pub fn win(&self) -> WIN_R

Bits 0:11 - Watchdog counter window value

impl R<u32, Reg<u32, _CR>>

pub fn wdga(&self) -> WDGA_R

Bit 7 - Activation bit

pub fn t(&self) -> T_R

Bits 0:6 - 7-bit counter (MSB to LSB)

impl R<u32, Reg<u32, _CFR>>

pub fn wdgtb(&self) -> WDGTB_R

Bits 11:13 - Timer base

pub fn ewi(&self) -> EWI_R

Bit 9 - Early wakeup interrupt

pub fn w(&self) -> W_R

Bits 0:6 - 7-bit window value

impl R<u32, Reg<u32, _SR>>

pub fn ewif(&self) -> EWIF_R

Bit 0 - Early wakeup interrupt flag

impl R<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1_en(&self) -> COMP1_EN_R

Bit 0 - Comparator enable

pub fn comp1_pwrmode(&self) -> COMP1_PWRMODE_R

Bits 2:3 - Comparator power mode

pub fn comp1_inmsel(&self) -> COMP1_INMSEL_R

Bits 4:6 - Comparator input minus selection

pub fn comp1_inpsel(&self) -> COMP1_INPSEL_R

Bits 7:8 - Comparator input plus selection

pub fn comp1_polarity(&self) -> COMP1_POLARITY_R

Bit 15 - Comparator output polarity

pub fn comp1_hyst(&self) -> COMP1_HYST_R

Bits 16:17 - Comparator hysteresis

pub fn comp1_blanking(&self) -> COMP1_BLANKING_R

Bits 18:20 - Comparator blanking source

pub fn comp1_brgen(&self) -> COMP1_BRGEN_R

Bit 22 - Comparator voltage scaler enable

pub fn comp1_scalen(&self) -> COMP1_SCALEN_R

Bit 23 - Comparator scaler bridge enable

pub fn comp1_inmesel(&self) -> COMP1_INMESEL_R

Bits 25:26 - Comparator input minus extended selection

pub fn comp1_value(&self) -> COMP1_VALUE_R

Bit 30 - Comparator output level

pub fn comp1_lock(&self) -> COMP1_LOCK_R

Bit 31 - Comparator lock

impl R<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2_en(&self) -> COMP2_EN_R

Bit 0 - Comparator 2 enable bit

pub fn comp2_pwrmode(&self) -> COMP2_PWRMODE_R

Bits 2:3 - Power Mode of the comparator 2

pub fn comp2_inmsel(&self) -> COMP2_INMSEL_R

Bits 4:5 - Comparator 2 input minus selection bits

pub fn comp2_inpsel(&self) -> COMP2_INPSEL_R

Bits 7:8 - Comparator 1 input plus selection bit

pub fn comp2_winmode(&self) -> COMP2_WINMODE_R

Bit 9 - Windows mode selection bit

pub fn comp2_polarity(&self) -> COMP2_POLARITY_R

Bit 15 - Comparator 2 polarity selection bit

pub fn comp2_hyst(&self) -> COMP2_HYST_R

Bits 16:17 - Comparator 2 hysteresis selection bits

pub fn comp2_blanking(&self) -> COMP2_BLANKING_R

Bits 18:20 - Comparator 2 blanking source selection bits

pub fn comp2_brgen(&self) -> COMP2_BRGEN_R

Bit 22 - Scaler bridge enable

pub fn comp2_scalen(&self) -> COMP2_SCALEN_R

Bit 23 - Voltage scaler enable bit

pub fn comp2_inmesel(&self) -> COMP2_INMESEL_R

Bits 25:26 - comparator 2 input minus extended selection bits.

pub fn comp2_value(&self) -> COMP2_VALUE_R

Bit 30 - Comparator 2 output status bit

pub fn comp2_lock(&self) -> COMP2_LOCK_R

Bit 31 - CSR register lock bit

impl R<u32, Reg<u32, _CR1>>

pub fn pe(&self) -> PE_R

Bit 0 - Peripheral enable

pub fn txie(&self) -> TXIE_R

Bit 1 - TX Interrupt enable

pub fn rxie(&self) -> RXIE_R

Bit 2 - RX Interrupt enable

pub fn addrie(&self) -> ADDRIE_R

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&self) -> NACKIE_R

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&self) -> STOPIE_R

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 7 - Error interrupts enable

pub fn dnf(&self) -> DNF_R

Bits 8:11 - Digital noise filter

pub fn anfoff(&self) -> ANFOFF_R

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 15 - DMA reception requests enable

pub fn sbc(&self) -> SBC_R

Bit 16 - Slave byte control

pub fn nostretch(&self) -> NOSTRETCH_R

Bit 17 - Clock stretching disable

pub fn wupen(&self) -> WUPEN_R

Bit 18 - Wakeup from STOP enable

pub fn gcen(&self) -> GCEN_R

Bit 19 - General call enable

pub fn smbhen(&self) -> SMBHEN_R

Bit 20 - SMBus Host address enable

pub fn smbden(&self) -> SMBDEN_R

Bit 21 - SMBus Device Default address enable

pub fn alerten(&self) -> ALERTEN_R

Bit 22 - SMBUS alert enable

pub fn pecen(&self) -> PECEN_R

Bit 23 - PEC enable

impl R<u32, Reg<u32, _CR2>>

pub fn pecbyte(&self) -> PECBYTE_R

Bit 26 - Packet error checking byte

pub fn autoend(&self) -> AUTOEND_R

Bit 25 - Automatic end mode (master mode)

pub fn reload(&self) -> RELOAD_R

Bit 24 - NBYTES reload mode

pub fn nbytes(&self) -> NBYTES_R

Bits 16:23 - Number of bytes

pub fn nack(&self) -> NACK_R

Bit 15 - NACK generation (slave mode)

pub fn stop(&self) -> STOP_R

Bit 14 - Stop generation (master mode)

pub fn start(&self) -> START_R

Bit 13 - Start generation

pub fn head10r(&self) -> HEAD10R_R

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&self) -> ADD10_R

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&self) -> RD_WRN_R

Bit 10 - Transfer direction (master mode)

pub fn sadd(&self) -> SADD_R

Bits 0:9 - Slave address bit (master mode)

impl R<u32, Reg<u32, _OAR1>>

pub fn oa1(&self) -> OA1_R

Bits 0:9 - Interface address

pub fn oa1mode(&self) -> OA1MODE_R

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&self) -> OA1EN_R

Bit 15 - Own Address 1 enable

impl R<u32, Reg<u32, _OAR2>>

pub fn oa2(&self) -> OA2_R

Bits 1:7 - Interface address

pub fn oa2msk(&self) -> OA2MSK_R

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&self) -> OA2EN_R

Bit 15 - Own Address 2 enable

impl R<u32, Reg<u32, _TIMINGR>>

pub fn scll(&self) -> SCLL_R

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&self) -> SCLH_R

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&self) -> SDADEL_R

Bits 16:19 - Data hold time

pub fn scldel(&self) -> SCLDEL_R

Bits 20:23 - Data setup time

pub fn presc(&self) -> PRESC_R

Bits 28:31 - Timing prescaler

impl R<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&self) -> TIMEOUTA_R

Bits 0:11 - Bus timeout A

pub fn tidle(&self) -> TIDLE_R

Bit 12 - Idle clock timeout detection

pub fn timouten(&self) -> TIMOUTEN_R

Bit 15 - Clock timeout enable

pub fn timeoutb(&self) -> TIMEOUTB_R

Bits 16:27 - Bus timeout B

pub fn texten(&self) -> TEXTEN_R

Bit 31 - Extended clock timeout enable

impl R<u32, Reg<u32, _ISR>>

pub fn addcode(&self) -> ADDCODE_R

Bits 17:23 - Address match code (Slave mode)

pub fn dir(&self) -> DIR_R

Bit 16 - Transfer direction (Slave mode)

pub fn busy(&self) -> BUSY_R

Bit 15 - Bus busy

pub fn alert(&self) -> ALERT_R

Bit 13 - SMBus alert

pub fn timeout(&self) -> TIMEOUT_R

Bit 12 - Timeout or t_low detection flag

pub fn pecerr(&self) -> PECERR_R

Bit 11 - PEC Error in reception

pub fn ovr(&self) -> OVR_R

Bit 10 - Overrun/Underrun (slave mode)

pub fn arlo(&self) -> ARLO_R

Bit 9 - Arbitration lost

pub fn berr(&self) -> BERR_R

Bit 8 - Bus error

pub fn tcr(&self) -> TCR_R

Bit 7 - Transfer Complete Reload

pub fn tc(&self) -> TC_R

Bit 6 - Transfer Complete (master mode)

pub fn stopf(&self) -> STOPF_R

Bit 5 - Stop detection flag

pub fn nackf(&self) -> NACKF_R

Bit 4 - Not acknowledge received flag

pub fn addr(&self) -> ADDR_R

Bit 3 - Address matched (slave mode)

pub fn rxne(&self) -> RXNE_R

Bit 2 - Receive data register not empty (receivers)

pub fn txis(&self) -> TXIS_R

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&self) -> TXE_R

Bit 0 - Transmit data register empty (transmitters)

impl R<u32, Reg<u32, _PECR>>

pub fn pec(&self) -> PEC_R

Bits 0:7 - Packet error checking register

impl R<u32, Reg<u32, _RXDR>>

pub fn rxdata(&self) -> RXDATA_R

Bits 0:7 - 8-bit receive data

impl R<u32, Reg<u32, _TXDR>>

pub fn txdata(&self) -> TXDATA_R

Bits 0:7 - 8-bit transmit data

impl R<u32, Reg<u32, _ACR>>

pub fn latency(&self) -> LATENCY_R

Bits 0:2 - Latency

pub fn prften(&self) -> PRFTEN_R

Bit 8 - Prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - Instruction cache enable

pub fn dcen(&self) -> DCEN_R

Bit 10 - Data cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - Instruction cache reset

pub fn dcrst(&self) -> DCRST_R

Bit 12 - Data cache reset

pub fn pes(&self) -> PES_R

Bit 15 - CPU1 CortexM4 program erase suspend request

pub fn empty(&self) -> EMPTY_R

Bit 16 - Flash User area empty

impl R<u32, Reg<u32, _SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - Write protected error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn miserr(&self) -> MISERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn optnv(&self) -> OPTNV_R

Bit 13 - User Option OPTVAL indication

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn optverr(&self) -> OPTVERR_R

Bit 15 - Option validity error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy

pub fn pesd(&self) -> PESD_R

Bit 19 - Programming or erase operation suspended

impl R<u32, Reg<u32, _CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - This bit triggers the mass erase (all user pages) when set

pub fn pnb(&self) -> PNB_R

Bits 3:10 - Page number selection

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn optstrt(&self) -> OPTSTRT_R

Bit 17 - Options modification start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&self) -> OBL_LAUNCH_R

Bit 27 - Force the option byte loading

pub fn optlock(&self) -> OPTLOCK_R

Bit 30 - Options Lock

pub fn lock(&self) -> LOCK_R

Bit 31 - FLASH_CR Lock

impl R<u32, Reg<u32, _ECCR>>

pub fn addr_ecc(&self) -> ADDR_ECC_R

Bits 0:16 - ECC fail address

pub fn sysf_ecc(&self) -> SYSF_ECC_R

Bit 20 - System Flash ECC fail

pub fn ecccie(&self) -> ECCCIE_R

Bit 24 - ECC correction interrupt enable

pub fn cpuid(&self) -> CPUID_R

Bits 26:28 - CPU identification

pub fn eccc(&self) -> ECCC_R

Bit 30 - ECC correction

pub fn eccd(&self) -> ECCD_R

Bit 31 - ECC detection

impl R<u32, Reg<u32, _OPTR>>

pub fn rdp(&self) -> RDP_R

Bits 0:7 - Read protection level

pub fn ese(&self) -> ESE_R

Bit 8 - Security enabled

pub fn bor_lev(&self) -> BOR_LEV_R

Bits 9:11 - BOR reset Level

pub fn n_rst_stop(&self) -> NRST_STOP_R

Bit 12 - nRST_STOP

pub fn n_rst_stdby(&self) -> NRST_STDBY_R

Bit 13 - nRST_STDBY

pub fn n_rst_shdw(&self) -> NRST_SHDW_R

Bit 14 - nRST_SHDW

pub fn idwg_sw(&self) -> IDWG_SW_R

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&self) -> IWDG_STOP_R

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&self) -> IWDG_STDBY_R

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&self) -> WWDG_SW_R

Bit 19 - Window watchdog selection

pub fn n_boot1(&self) -> NBOOT1_R

Bit 23 - Boot configuration

pub fn sram2_pe(&self) -> SRAM2_PE_R

Bit 24 - SRAM2 parity check enable

pub fn sram2_rst(&self) -> SRAM2_RST_R

Bit 25 - SRAM2 Erase when system reset

pub fn n_swboot0(&self) -> NSWBOOT0_R

Bit 26 - Software Boot0

pub fn n_boot0(&self) -> NBOOT0_R

Bit 27 - nBoot0 option bit

pub fn agc_trim(&self) -> AGC_TRIM_R

Bits 29:31 - Radio Automatic Gain Control Trimming

impl R<u32, Reg<u32, _PCROP1ASR>>

pub fn pcrop1a_strt(&self) -> PCROP1A_STRT_R

Bits 0:8 - Bank 1 PCROPQ area start offset

impl R<u32, Reg<u32, _PCROP1AER>>

pub fn pcrop1a_end(&self) -> PCROP1A_END_R

Bits 0:8 - Bank 1 PCROP area end offset

pub fn pcrop_rdp(&self) -> PCROP_RDP_R

Bit 31 - PCROP area preserved when RDP level decreased

impl R<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&self) -> WRP1A_STRT_R

Bits 0:7 - Bank 1 WRP first area A start offset

pub fn wrp1a_end(&self) -> WRP1A_END_R

Bits 16:23 - Bank 1 WRP first area A end offset

impl R<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&self) -> WRP1B_STRT_R

Bits 16:23 - Bank 1 WRP second area B end offset

pub fn wrp1b_end(&self) -> WRP1B_END_R

Bits 0:7 - Bank 1 WRP second area B start offset

impl R<u32, Reg<u32, _PCROP1BSR>>

pub fn pcrop1b_strt(&self) -> PCROP1B_STRT_R

Bits 0:8 - Bank 1 PCROP area B start offset

impl R<u32, Reg<u32, _PCROP1BER>>

pub fn pcrop1b_end(&self) -> PCROP1B_END_R

Bits 0:8 - Bank 1 PCROP area end area B offset

impl R<u32, Reg<u32, _IPCCBR>>

pub fn ipccdba(&self) -> IPCCDBA_R

Bits 0:13 - PCC mailbox data buffer base address

impl R<u32, Reg<u32, _C2ACR>>

pub fn prften(&self) -> PRFTEN_R

Bit 8 - CPU2 cortex M0 prefetch enable

pub fn icen(&self) -> ICEN_R

Bit 9 - CPU2 cortex M0 instruction cache enable

pub fn icrst(&self) -> ICRST_R

Bit 11 - CPU2 cortex M0 instruction cache reset

pub fn pes(&self) -> PES_R

Bit 15 - CPU2 cortex M0 program erase suspend request

impl R<u32, Reg<u32, _C2SR>>

pub fn eop(&self) -> EOP_R

Bit 0 - End of operation

pub fn operr(&self) -> OPERR_R

Bit 1 - Operation error

pub fn progerr(&self) -> PROGERR_R

Bit 3 - Programming error

pub fn wrperr(&self) -> WRPERR_R

Bit 4 - write protection error

pub fn pgaerr(&self) -> PGAERR_R

Bit 5 - Programming alignment error

pub fn sizerr(&self) -> SIZERR_R

Bit 6 - Size error

pub fn pgserr(&self) -> PGSERR_R

Bit 7 - Programming sequence error

pub fn misserr(&self) -> MISSERR_R

Bit 8 - Fast programming data miss error

pub fn fasterr(&self) -> FASTERR_R

Bit 9 - Fast programming error

pub fn rderr(&self) -> RDERR_R

Bit 14 - PCROP read error

pub fn bsy(&self) -> BSY_R

Bit 16 - Busy

pub fn cfgbsy(&self) -> CFGBSY_R

Bit 18 - Programming or erase configuration busy

pub fn pesd(&self) -> PESD_R

Bit 19 - Programming or erase operation suspended

impl R<u32, Reg<u32, _C2CR>>

pub fn pg(&self) -> PG_R

Bit 0 - Programming

pub fn per(&self) -> PER_R

Bit 1 - Page erase

pub fn mer(&self) -> MER_R

Bit 2 - Masse erase

pub fn pnb(&self) -> PNB_R

Bits 3:10 - Page Number selection

pub fn strt(&self) -> STRT_R

Bit 16 - Start

pub fn fstpg(&self) -> FSTPG_R

Bit 18 - Fast programming

pub fn eopie(&self) -> EOPIE_R

Bit 24 - End of operation interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 25 - Error interrupt enable

pub fn rderrie(&self) -> RDERRIE_R

Bit 26 - PCROP read error interrupt enable

impl R<u32, Reg<u32, _SFR>>

pub fn sfsa(&self) -> SFSA_R

Bits 0:7 - Secure flash start address

pub fn dds(&self) -> DDS_R

Bit 12 - Disable Cortex M0 debug access

pub fn fsd(&self) -> FSD_R

Bit 8 - Flash security disable

impl R<u32, Reg<u32, _SRRVR>>

pub fn sbrv(&self) -> SBRV_R

Bits 0:17 - cortex M0 access control register

pub fn sbrsa(&self) -> SBRSA_R

Bits 18:22 - Secure backup SRAM2a start address

pub fn brsd(&self) -> BRSD_R

Bit 23 - backup SRAM2a security disable

pub fn snbrsa(&self) -> SNBRSA_R

Bits 25:29 - Secure non backup SRAM2a start address

pub fn c2opt(&self) -> C2OPT_R

Bit 31 - CPU2 cortex M0 boot reset vector memory selection

pub fn nbrsd(&self) -> NBRSD_R

Bit 30 - non-backup SRAM2b security disable

impl R<u32, Reg<u32, _CR>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 24:31 - Clock prescaler

pub fn pmm(&self) -> PMM_R

Bit 23 - Polling match mode

pub fn apms(&self) -> APMS_R

Bit 22 - Automatic poll mode stop

pub fn toie(&self) -> TOIE_R

Bit 20 - TimeOut interrupt enable

pub fn smie(&self) -> SMIE_R

Bit 19 - Status match interrupt enable

pub fn ftie(&self) -> FTIE_R

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 17 - Transfer complete interrupt enable

pub fn teie(&self) -> TEIE_R

Bit 16 - Transfer error interrupt enable

pub fn fthres(&self) -> FTHRES_R

Bits 8:11 - FIFO threshold level

pub fn sshift(&self) -> SSHIFT_R

Bit 4 - Sample shift

pub fn tcen(&self) -> TCEN_R

Bit 3 - Timeout counter enable

pub fn dmaen(&self) -> DMAEN_R

Bit 2 - DMA enable

pub fn abort(&self) -> ABORT_R

Bit 1 - Abort request

pub fn en(&self) -> EN_R

Bit 0 - Enable

impl R<u32, Reg<u32, _DCR>>

pub fn fsize(&self) -> FSIZE_R

Bits 16:20 - FLASH memory size

pub fn csht(&self) -> CSHT_R

Bits 8:10 - Chip select high time

pub fn ckmode(&self) -> CKMODE_R

Bit 0 - Mode 0 / mode 3

impl R<u32, Reg<u32, _SR>>

pub fn flevel(&self) -> FLEVEL_R

Bits 8:12 - FIFO level

pub fn busy(&self) -> BUSY_R

Bit 5 - Busy

pub fn tof(&self) -> TOF_R

Bit 4 - Timeout flag

pub fn smf(&self) -> SMF_R

Bit 3 - Status match flag

pub fn ftf(&self) -> FTF_R

Bit 2 - FIFO threshold flag

pub fn tcf(&self) -> TCF_R

Bit 1 - Transfer complete flag

pub fn tef(&self) -> TEF_R

Bit 0 - Transfer error flag

impl R<u32, Reg<u32, _FCR>>

pub fn ctof(&self) -> CTOF_R

Bit 4 - Clear timeout flag

pub fn csmf(&self) -> CSMF_R

Bit 3 - Clear status match flag

pub fn ctcf(&self) -> CTCF_R

Bit 1 - Clear transfer complete flag

pub fn ctef(&self) -> CTEF_R

Bit 0 - Clear transfer error flag

impl R<u32, Reg<u32, _DLR>>

pub fn dl(&self) -> DL_R

Bits 0:31 - Data length

impl R<u32, Reg<u32, _CCR>>

pub fn ddrm(&self) -> DDRM_R

Bit 31 - Double data rate mode

pub fn sioo(&self) -> SIOO_R

Bit 28 - Send instruction only once mode

pub fn fmode(&self) -> FMODE_R

Bits 26:27 - Functional mode

pub fn dmode(&self) -> DMODE_R

Bits 24:25 - Data mode

pub fn dcyc(&self) -> DCYC_R

Bits 18:22 - Number of dummy cycles

pub fn absize(&self) -> ABSIZE_R

Bits 16:17 - Alternate bytes size

pub fn abmode(&self) -> ABMODE_R

Bits 14:15 - Alternate bytes mode

pub fn adsize(&self) -> ADSIZE_R

Bits 12:13 - Address size

pub fn admode(&self) -> ADMODE_R

Bits 10:11 - Address mode

pub fn imode(&self) -> IMODE_R

Bits 8:9 - Instruction mode

pub fn instruction(&self) -> INSTRUCTION_R

Bits 0:7 - Instruction

impl R<u32, Reg<u32, _AR>>

pub fn address(&self) -> ADDRESS_R

Bits 0:31 - Address

impl R<u32, Reg<u32, _ABR>>

pub fn alternate(&self) -> ALTERNATE_R

Bits 0:31 - ALTERNATE

impl R<u32, Reg<u32, _DR>>

pub fn data(&self) -> DATA_R

Bits 0:31 - Data

impl R<u32, Reg<u32, _PSMKR>>

pub fn mask(&self) -> MASK_R

Bits 0:31 - Status mask

impl R<u32, Reg<u32, _PSMAR>>

pub fn match_(&self) -> MATCH_R

Bits 0:31 - Status match

impl R<u32, Reg<u32, _PIR>>

pub fn interval(&self) -> INTERVAL_R

Bits 0:15 - Polling interval

impl R<u32, Reg<u32, _LPTR>>

pub fn timeout(&self) -> TIMEOUT_R

Bits 0:15 - Timeout period

impl R<u32, Reg<u32, _CR>>

pub fn pllsai1rdy(&self) -> PLLSAI1RDY_R

Bit 27 - SAI1 PLL clock ready flag

pub fn pllsai1on(&self) -> PLLSAI1ON_R

Bit 26 - SAI1 PLL enable

pub fn pllrdy(&self) -> PLLRDY_R

Bit 25 - Main PLL clock ready flag

pub fn pllon(&self) -> PLLON_R

Bit 24 - Main PLL enable

pub fn hsepre(&self) -> HSEPRE_R

Bit 20 - HSE sysclk and PLL M divider prescaler

pub fn hsebyp(&self) -> HSEBYP_R

Bit 18 - HSE crystal oscillator bypass

pub fn hserdy(&self) -> HSERDY_R

Bit 17 - HSE clock ready flag

pub fn hseon(&self) -> HSEON_R

Bit 16 - HSE clock enabled

pub fn hsikerdy(&self) -> HSIKERDY_R

Bit 12 - HSI kernel clock ready flag for peripherals requests

pub fn hsiasfs(&self) -> HSIASFS_R

Bit 11 - HSI automatic start from Stop

pub fn hsirdy(&self) -> HSIRDY_R

Bit 10 - HSI clock ready flag

pub fn hsikeron(&self) -> HSIKERON_R

Bit 9 - HSI always enable for peripheral kernels

pub fn hsion(&self) -> HSION_R

Bit 8 - HSI clock enabled

pub fn msirange(&self) -> MSIRANGE_R

Bits 4:7 - MSI clock ranges

pub fn msipllen(&self) -> MSIPLLEN_R

Bit 2 - MSI clock PLL enable

pub fn msirdy(&self) -> MSIRDY_R

Bit 1 - MSI clock ready flag

pub fn msion(&self) -> MSION_R

Bit 0 - MSI clock enable

impl R<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&self) -> HSITRIM_R

Bits 24:30 - HSI clock trimming

pub fn hsical(&self) -> HSICAL_R

Bits 16:23 - HSI clock calibration

pub fn msitrim(&self) -> MSITRIM_R

Bits 8:15 - MSI clock trimming

pub fn msical(&self) -> MSICAL_R

Bits 0:7 - MSI clock calibration

impl R<u32, Reg<u32, _CFGR>>

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller clock output prescaler

pub fn mcosel(&self) -> MCOSEL_R

Bits 24:27 - Microcontroller clock output

pub fn ppre2f(&self) -> PPRE2F_R

Bit 18 - APB2 prescaler flag

pub fn ppre1f(&self) -> PPRE1F_R

Bit 17 - APB1 prescaler flag

pub fn hpref(&self) -> HPREF_R

Bit 16 - AHB prescaler flag

pub fn stopwuck(&self) -> STOPWUCK_R

Bit 15 - Wakeup from Stop and CSS backup clock selection

pub fn ppre2(&self) -> PPRE2_R

Bits 11:13 - APB high-speed prescaler (APB2)

pub fn ppre1(&self) -> PPRE1_R

Bits 8:10 - PB low-speed prescaler (APB1)

pub fn hpre(&self) -> HPRE_R

Bits 4:7 - AHB prescaler

pub fn sws(&self) -> SWS_R

Bits 2:3 - System clock switch status

pub fn sw(&self) -> SW_R

Bits 0:1 - System clock switch

impl R<u32, Reg<u32, _PLLCFGR>>

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)

pub fn pllren(&self) -> PLLREN_R

Bit 28 - Main PLLSYSR PLLCLK output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - Main PLLSYSQ output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - Main PLLSYSP output enable

pub fn plln(&self) -> PLLN_R

Bits 8:14 - Main PLLSYS multiplication factor N

pub fn pllm(&self) -> PLLM_R

Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

impl R<u32, Reg<u32, _PLLSAI1CFGR>>

pub fn pllr(&self) -> PLLR_R

Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)

pub fn pllren(&self) -> PLLREN_R

Bit 28 - PLLSAI PLLADC1CLK output enable

pub fn pllq(&self) -> PLLQ_R

Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)

pub fn pllqen(&self) -> PLLQEN_R

Bit 24 - SAIPLL PLLSAIUSBCLK output enable

pub fn pllp(&self) -> PLLP_R

Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - SAIPLL PLLSAI1CLK output enable

pub fn plln(&self) -> PLLN_R

Bits 8:14 - SAIPLL multiplication factor for VCO

impl R<u32, Reg<u32, _CIER>>

pub fn lsi2rdyie(&self) -> LSI2RDYIE_R

Bit 11 - LSI2 ready interrupt enable

pub fn hsi48rdyie(&self) -> HSI48RDYIE_R

Bit 10 - HSI48 ready interrupt enable

pub fn lsecssie(&self) -> LSECSSIE_R

Bit 9 - LSE clock security system interrupt enable

pub fn pllsai1rdyie(&self) -> PLLSAI1RDYIE_R

Bit 6 - PLLSAI1 ready interrupt enable

pub fn pllrdyie(&self) -> PLLRDYIE_R

Bit 5 - PLLSYS ready interrupt enable

pub fn hserdyie(&self) -> HSERDYIE_R

Bit 4 - HSE ready interrupt enable

pub fn hsirdyie(&self) -> HSIRDYIE_R

Bit 3 - HSI ready interrupt enable

pub fn msirdyie(&self) -> MSIRDYIE_R

Bit 2 - MSI ready interrupt enable

pub fn lserdyie(&self) -> LSERDYIE_R

Bit 1 - LSE ready interrupt enable

pub fn lsi1rdyie(&self) -> LSI1RDYIE_R

Bit 0 - LSI1 ready interrupt enable

impl R<u32, Reg<u32, _CIFR>>

pub fn lsi2rdyf(&self) -> LSI2RDYF_R

Bit 11 - LSI2 ready interrupt flag

pub fn hsi48rdyf(&self) -> HSI48RDYF_R

Bit 10 - HSI48 ready interrupt flag

pub fn lsecssf(&self) -> LSECSSF_R

Bit 9 - LSE Clock security system interrupt flag

pub fn hsecssf(&self) -> HSECSSF_R

Bit 8 - HSE Clock security system interrupt flag

pub fn pllsai1rdyf(&self) -> PLLSAI1RDYF_R

Bit 6 - PLLSAI1 ready interrupt flag

pub fn pllrdyf(&self) -> PLLRDYF_R

Bit 5 - PLL ready interrupt flag

pub fn hserdyf(&self) -> HSERDYF_R

Bit 4 - HSE ready interrupt flag

pub fn hsirdyf(&self) -> HSIRDYF_R

Bit 3 - HSI ready interrupt flag

pub fn msirdyf(&self) -> MSIRDYF_R

Bit 2 - MSI ready interrupt flag

pub fn lserdyf(&self) -> LSERDYF_R

Bit 1 - LSE ready interrupt flag

pub fn lsi1rdyf(&self) -> LSI1RDYF_R

Bit 0 - LSI1 ready interrupt flag

impl R<u32, Reg<u32, _SMPSCR>>

pub fn smpssws(&self) -> SMPSSWS_R

Bits 8:9 - Step Down converter clock switch status

pub fn smpsdiv(&self) -> SMPSDIV_R

Bits 4:5 - Step Down converter clock prescaler

pub fn smpssel(&self) -> SMPSSEL_R

Bits 0:1 - Step Down converter clock selection

impl R<u32, Reg<u32, _AHB1RSTR>>

pub fn tscrst(&self) -> TSCRST_R

Bit 16 - Touch Sensing Controller reset

pub fn crcrst(&self) -> CRCRST_R

Bit 12 - CRC reset

pub fn dmamuxrst(&self) -> DMAMUXRST_R

Bit 2 - DMAMUX reset

pub fn dma2rst(&self) -> DMA2RST_R

Bit 1 - DMA2 reset

pub fn dma1rst(&self) -> DMA1RST_R

Bit 0 - DMA1 reset

impl R<u32, Reg<u32, _AHB2RSTR>>

pub fn aes1rst(&self) -> AES1RST_R

Bit 16 - AES1 hardware accelerator reset

pub fn adcrst(&self) -> ADCRST_R

Bit 13 - ADC reset

pub fn gpiohrst(&self) -> GPIOHRST_R

Bit 7 - IO port H reset

pub fn gpioerst(&self) -> GPIOERST_R

Bit 4 - IO port E reset

pub fn gpiodrst(&self) -> GPIODRST_R

Bit 3 - IO port D reset

pub fn gpiocrst(&self) -> GPIOCRST_R

Bit 2 - IO port C reset

pub fn gpiobrst(&self) -> GPIOBRST_R

Bit 1 - IO port B reset

pub fn gpioarst(&self) -> GPIOARST_R

Bit 0 - IO port A reset

impl R<u32, Reg<u32, _AHB3RSTR>>

pub fn flashrst(&self) -> FLASHRST_R

Bit 25 - Flash interface reset

pub fn ipccrst(&self) -> IPCCRST_R

Bit 20 - IPCC interface reset

pub fn hsemrst(&self) -> HSEMRST_R

Bit 19 - HSEM interface reset

pub fn rngrst(&self) -> RNGRST_R

Bit 18 - RNG interface reset

pub fn aes2rst(&self) -> AES2RST_R

Bit 17 - AES2 interface reset

pub fn pkarst(&self) -> PKARST_R

Bit 16 - PKA interface reset

pub fn qspirst(&self) -> QSPIRST_R

Bit 8 - Quad SPI memory interface reset

impl R<u32, Reg<u32, _APB1RSTR1>>

pub fn lptim1rst(&self) -> LPTIM1RST_R

Bit 31 - Low Power Timer 1 reset

pub fn usbfsrst(&self) -> USBFSRST_R

Bit 26 - USB FS reset

pub fn crsrst(&self) -> CRSRST_R

Bit 24 - CRS reset

pub fn i2c3rst(&self) -> I2C3RST_R

Bit 23 - I2C3 reset

pub fn i2c1rst(&self) -> I2C1RST_R

Bit 21 - I2C1 reset

pub fn spi2rst(&self) -> SPI2RST_R

Bit 14 - SPI2 reset

pub fn lcdrst(&self) -> LCDRST_R

Bit 9 - LCD interface reset

pub fn tim2rst(&self) -> TIM2RST_R

Bit 0 - TIM2 timer reset

impl R<u32, Reg<u32, _APB1RSTR2>>

pub fn lptim2rst(&self) -> LPTIM2RST_R

Bit 5 - Low-power timer 2 reset

pub fn lpuart1rst(&self) -> LPUART1RST_R

Bit 0 - Low-power UART 1 reset

impl R<u32, Reg<u32, _APB2RSTR>>

pub fn sai1rst(&self) -> SAI1RST_R

Bit 21 - Serial audio interface 1 (SAI1) reset

pub fn tim17rst(&self) -> TIM17RST_R

Bit 18 - TIM17 timer reset

pub fn tim16rst(&self) -> TIM16RST_R

Bit 17 - TIM16 timer reset

pub fn usart1rst(&self) -> USART1RST_R

Bit 14 - USART1 reset

pub fn spi1rst(&self) -> SPI1RST_R

Bit 12 - SPI1 reset

pub fn tim1rst(&self) -> TIM1RST_R

Bit 11 - TIM1 timer reset

impl R<u32, Reg<u32, _APB3RSTR>>

pub fn rfrst(&self) -> RFRST_R

Bit 0 - Radio system BLE reset

impl R<u32, Reg<u32, _AHB1ENR>>

pub fn tscen(&self) -> TSCEN_R

Bit 16 - Touch Sensing Controller clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CPU1 CRC clock enable

pub fn dmamuxen(&self) -> DMAMUXEN_R

Bit 2 - DMAMUX clock enable

pub fn dma2en(&self) -> DMA2EN_R

Bit 1 - DMA2 clock enable

pub fn dma1en(&self) -> DMA1EN_R

Bit 0 - DMA1 clock enable

impl R<u32, Reg<u32, _AHB2ENR>>

pub fn aes1en(&self) -> AES1EN_R

Bit 16 - AES1 accelerator clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 13 - ADC clock enable

pub fn gpiohen(&self) -> GPIOHEN_R

Bit 7 - IO port H clock enable

pub fn gpioeen(&self) -> GPIOEEN_R

Bit 4 - IO port E clock enable

pub fn gpioden(&self) -> GPIODEN_R

Bit 3 - IO port D clock enable

pub fn gpiocen(&self) -> GPIOCEN_R

Bit 2 - IO port C clock enable

pub fn gpioben(&self) -> GPIOBEN_R

Bit 1 - IO port B clock enable

pub fn gpioaen(&self) -> GPIOAEN_R

Bit 0 - IO port A clock enable

impl R<u32, Reg<u32, _AHB3ENR>>

pub fn flashen(&self) -> FLASHEN_R

Bit 25 - FLASHEN

pub fn ipccen(&self) -> IPCCEN_R

Bit 20 - IPCCEN

pub fn hsemen(&self) -> HSEMEN_R

Bit 19 - HSEMEN

pub fn rngen(&self) -> RNGEN_R

Bit 18 - RNGEN

pub fn aes2en(&self) -> AES2EN_R

Bit 17 - AES2EN

pub fn pkaen(&self) -> PKAEN_R

Bit 16 - PKAEN

pub fn qspien(&self) -> QSPIEN_R

Bit 8 - QSPIEN

impl R<u32, Reg<u32, _APB1ENR1>>

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - CPU1 Low power timer 1 clock enable

pub fn usben(&self) -> USBEN_R

Bit 26 - CPU1 USB clock enable

pub fn crsen(&self) -> CRSEN_R

Bit 24 - CPU1 CRS clock enable

pub fn i2c3en(&self) -> I2C3EN_R

Bit 23 - CPU1 I2C3 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - CPU1 I2C1 clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - CPU1 SPI2 clock enable

pub fn wwdgen(&self) -> WWDGEN_R

Bit 11 - CPU1 Window watchdog clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - CPU1 RTC APB clock enable

pub fn lcden(&self) -> LCDEN_R

Bit 9 - CPU1 LCD clock enable

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - CPU1 TIM2 timer clock enable

impl R<u32, Reg<u32, _APB1ENR2>>

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 5 - CPU1 LPTIM2EN

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 0 - CPU1 Low power UART 1 clock enable

impl R<u32, Reg<u32, _APB2ENR>>

pub fn sai1en(&self) -> SAI1EN_R

Bit 21 - CPU1 SAI1 clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - CPU1 TIM17 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - CPU1 TIM16 timer clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - CPU1 USART1clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - CPU1 SPI1 clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - CPU1 TIM1 timer clock enable

impl R<u32, Reg<u32, _AHB1SMENR>>

pub fn tscsmen(&self) -> TSCSMEN_R

Bit 16 - CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CPU1 CRCSMEN

pub fn sram1smen(&self) -> SRAM1SMEN_R

Bit 9 - CPU1 SRAM1 interface clocks enable during Sleep and Stop modes

pub fn dmamuxsmen(&self) -> DMAMUXSMEN_R

Bit 2 - CPU1 DMAMUX clocks enable during Sleep and Stop modes

pub fn dma2smen(&self) -> DMA2SMEN_R

Bit 1 - CPU1 DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&self) -> DMA1SMEN_R

Bit 0 - CPU1 DMA1 clocks enable during Sleep and Stop modes

impl R<u32, Reg<u32, _AHB2SMENR>>

pub fn aes1smen(&self) -> AES1SMEN_R

Bit 16 - CPU1 AES1 accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&self) -> ADCFSSMEN_R

Bit 13 - CPU1 ADC clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&self) -> GPIOHSMEN_R

Bit 7 - CPU1 IO port H clocks enable during Sleep and Stop modes

pub fn gpioesmen(&self) -> GPIOESMEN_R

Bit 4 - CPU1 IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&self) -> GPIODSMEN_R

Bit 3 - CPU1 IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&self) -> GPIOCSMEN_R

Bit 2 - CPU1 IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&self) -> GPIOBSMEN_R

Bit 1 - CPU1 IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&self) -> GPIOASMEN_R

Bit 0 - CPU1 IO port A clocks enable during Sleep and Stop modes

impl R<u32, Reg<u32, _AHB3SMENR>>

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 25 - Flash interface clocks enable during CPU1 sleep mode

pub fn sram2smen(&self) -> SRAM2SMEN_R

Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode

pub fn rngsmen(&self) -> RNGSMEN_R

Bit 18 - True RNG clocks enable during CPU1 sleep mode

pub fn aes2smen(&self) -> AES2SMEN_R

Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode

pub fn pkasmen(&self) -> PKASMEN_R

Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode

pub fn qspismen(&self) -> QSPISMEN_R

Bit 8 - QSPISMEN

impl R<u32, Reg<u32, _APB1SMENR1>>

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low power timer 1 clocks enable during CPU1 Sleep mode

pub fn usbsmen(&self) -> USBSMEN_R

Bit 26 - USB FS clocks enable during CPU1 Sleep mode

pub fn crsmen(&self) -> CRSMEN_R

Bit 24 - CRS clocks enable during CPU1 Sleep mode

pub fn i2c3smen(&self) -> I2C3SMEN_R

Bit 23 - I2C3 clocks enable during CPU1 Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clocks enable during CPU1 Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clocks enable during CPU1 Sleep mode

pub fn wwdgsmen(&self) -> WWDGSMEN_R

Bit 11 - Window watchdog clocks enable during CPU1 Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clocks enable during CPU1 Sleep mode

pub fn lcdsmen(&self) -> LCDSMEN_R

Bit 9 - LCD clocks enable during CPU1 Sleep mode

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clocks enable during CPU1 Sleep mode

impl R<u32, Reg<u32, _APB1SMENR2>>

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 5 - Low power timer 2 clocks enable during CPU1 Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 0 - Low power UART 1 clocks enable during CPU1 Sleep mode

impl R<u32, Reg<u32, _APB2SMENR>>

pub fn sai1smen(&self) -> SAI1SMEN_R

Bit 21 - SAI1 clocks enable during CPU1 Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM17 timer clocks enable during CPU1 Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clocks enable during CPU1 Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1clocks enable during CPU1 Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clocks enable during CPU1 Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clocks enable during CPU1 Sleep mode

impl R<u32, Reg<u32, _CCIPR>>

pub fn rngsel(&self) -> RNGSEL_R

Bits 30:31 - RNG clock source selection

pub fn adcsel(&self) -> ADCSEL_R

Bits 28:29 - ADCs clock source selection

pub fn clk48sel(&self) -> CLK48SEL_R

Bits 26:27 - 48 MHz clock source selection

pub fn sai1sel(&self) -> SAI1SEL_R

Bits 22:23 - SAI1 clock source selection

pub fn lptim2sel(&self) -> LPTIM2SEL_R

Bits 20:21 - Low power timer 2 clock source selection

pub fn lptim1sel(&self) -> LPTIM1SEL_R

Bits 18:19 - Low power timer 1 clock source selection

pub fn i2c3sel(&self) -> I2C3SEL_R

Bits 16:17 - I2C3 clock source selection

pub fn i2c1sel(&self) -> I2C1SEL_R

Bits 12:13 - I2C1 clock source selection

pub fn lpuart1sel(&self) -> LPUART1SEL_R

Bits 10:11 - LPUART1 clock source selection

pub fn usart1sel(&self) -> USART1SEL_R

Bits 0:1 - USART1 clock source selection

impl R<u32, Reg<u32, _BDCR>>

pub fn lscosel(&self) -> LSCOSEL_R

Bits 25:26 - Low speed clock output selection

pub fn lscoen(&self) -> LSCOEN_R

Bit 24 - Low speed clock output enable

pub fn bdrst(&self) -> BDRST_R

Bit 16 - Backup domain software reset

pub fn rtcen(&self) -> RTCEN_R

Bit 15 - RTC clock enable

pub fn rtcsel(&self) -> RTCSEL_R

Bits 8:9 - RTC clock source selection

pub fn lsecssd_(&self) -> LSECSSD__R

Bit 6 - CSS on LSE failure detection

pub fn lsecsson(&self) -> LSECSSON_R

Bit 5 - LSECSSON

pub fn lsedrv(&self) -> LSEDRV_R

Bits 3:4 - SE oscillator drive capability

pub fn lsebyp(&self) -> LSEBYP_R

Bit 2 - LSE oscillator bypass

pub fn lserdy(&self) -> LSERDY_R

Bit 1 - LSE oscillator ready

pub fn lseon(&self) -> LSEON_R

Bit 0 - LSE oscillator enable

impl R<u32, Reg<u32, _CSR>>

pub fn lpwrrstf(&self) -> LPWRRSTF_R

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&self) -> WWDGRSTF_R

Bit 30 - Window watchdog reset flag

pub fn iwdgrstf(&self) -> IWDGRSTF_R

Bit 29 - Independent window watchdog reset flag

pub fn sftrstf(&self) -> SFTRSTF_R

Bit 28 - Software reset flag

pub fn borrstf(&self) -> BORRSTF_R

Bit 27 - BOR flag

pub fn pinrstf(&self) -> PINRSTF_R

Bit 26 - Pin reset flag

pub fn oblrstf(&self) -> OBLRSTF_R

Bit 25 - Option byte loader reset flag

pub fn rmvf(&self) -> RMVF_R

Bit 23 - Remove reset flag

pub fn rfwkpsel(&self) -> RFWKPSEL_R

Bits 14:15 - RF system wakeup clock source selection

pub fn lsi2bw(&self) -> LSI2BW_R

Bits 8:11 - LSI2 oscillator bias configuration

pub fn lsi2trimok(&self) -> LSI2TRIMOK_R

Bit 5 - LSI2 oscillator trim OK

pub fn lsi2trimen(&self) -> LSI2TRIMEN_R

Bit 4 - LSI2 oscillator trimming enable

pub fn lsi2rdy(&self) -> LSI2RDY_R

Bit 3 - LSI2 oscillator ready

pub fn lsi2on(&self) -> LSI2ON_R

Bit 2 - LSI2 oscillator enabled

pub fn lsi1rdy(&self) -> LSI1RDY_R

Bit 1 - LSI1 oscillator ready

pub fn lsi1on(&self) -> LSI1ON_R

Bit 0 - LSI1 oscillator enabled

pub fn rfrsts(&self) -> RFRSTS_R

Bit 16 - Radio system BLE and 802.15.4 reset status

impl R<u32, Reg<u32, _CRRCR>>

pub fn hsi48cal(&self) -> HSI48CAL_R

Bits 7:15 - HSI48 clock calibration

pub fn hsi48rdy(&self) -> HSI48RDY_R

Bit 1 - HSI48 clock ready

pub fn hsi48on(&self) -> HSI48ON_R

Bit 0 - HSI48 oscillator enabled

impl R<u32, Reg<u32, _HSECR>>

pub fn hsetune(&self) -> HSETUNE_R

Bits 8:13 - HSE capacitor tuning

pub fn hsegmc(&self) -> HSEGMC_R

Bits 4:6 - HSE current control

pub fn hses(&self) -> HSES_R

Bit 3 - HSE Sense amplifier threshold

pub fn unlocked(&self) -> UNLOCKED_R

Bit 0 - Register lock system

impl R<u32, Reg<u32, _EXTCFGR>>

pub fn rfcss(&self) -> RFCSS_R

Bit 20 - RF clock source selected

pub fn c2hpref(&self) -> C2HPREF_R

Bit 17 - CPU2 AHB prescaler flag

pub fn shdhpref(&self) -> SHDHPREF_R

Bit 16 - Shared AHB prescaler flag

pub fn c2hpre(&self) -> C2HPRE_R

Bits 4:7 - CPU2 AHB prescaler

pub fn shdhpre(&self) -> SHDHPRE_R

Bits 0:3 - Shared AHB prescaler

impl R<u32, Reg<u32, _C2AHB1ENR>>

pub fn tscen(&self) -> TSCEN_R

Bit 16 - CPU2 Touch Sensing Controller clock enable

pub fn crcen(&self) -> CRCEN_R

Bit 12 - CPU2 CRC clock enable

pub fn sram1en(&self) -> SRAM1EN_R

Bit 9 - CPU2 SRAM1 clock enable

pub fn dmamuxen(&self) -> DMAMUXEN_R

Bit 2 - CPU2 DMAMUX clock enable

pub fn dma2en(&self) -> DMA2EN_R

Bit 1 - CPU2 DMA2 clock enable

pub fn dma1en(&self) -> DMA1EN_R

Bit 0 - CPU2 DMA1 clock enable

impl R<u32, Reg<u32, _C2AHB2ENR>>

pub fn aes1en(&self) -> AES1EN_R

Bit 16 - CPU2 AES1 accelerator clock enable

pub fn adcen(&self) -> ADCEN_R

Bit 13 - CPU2 ADC clock enable

pub fn gpiohen(&self) -> GPIOHEN_R

Bit 7 - CPU2 IO port H clock enable

pub fn gpioeen(&self) -> GPIOEEN_R

Bit 4 - CPU2 IO port E clock enable

pub fn gpioden(&self) -> GPIODEN_R

Bit 3 - CPU2 IO port D clock enable

pub fn gpiocen(&self) -> GPIOCEN_R

Bit 2 - CPU2 IO port C clock enable

pub fn gpioben(&self) -> GPIOBEN_R

Bit 1 - CPU2 IO port B clock enable

pub fn gpioaen(&self) -> GPIOAEN_R

Bit 0 - CPU2 IO port A clock enable

impl R<u32, Reg<u32, _C2AHB3ENR>>

pub fn flashen(&self) -> FLASHEN_R

Bit 25 - CPU2 FLASHEN

pub fn ipccen(&self) -> IPCCEN_R

Bit 20 - CPU2 IPCCEN

pub fn hsemen(&self) -> HSEMEN_R

Bit 19 - CPU2 HSEMEN

pub fn rngen(&self) -> RNGEN_R

Bit 18 - CPU2 RNGEN

pub fn aes2en(&self) -> AES2EN_R

Bit 17 - CPU2 AES2EN

pub fn pkaen(&self) -> PKAEN_R

Bit 16 - CPU2 PKAEN

impl R<u32, Reg<u32, _C2APB1ENR1>>

pub fn lptim1en(&self) -> LPTIM1EN_R

Bit 31 - CPU2 Low power timer 1 clock enable

pub fn usben(&self) -> USBEN_R

Bit 26 - CPU2 USB clock enable

pub fn crsen(&self) -> CRSEN_R

Bit 24 - CPU2 CRS clock enable

pub fn i2c3en(&self) -> I2C3EN_R

Bit 23 - CPU2 I2C3 clock enable

pub fn i2c1en(&self) -> I2C1EN_R

Bit 21 - CPU2 I2C1 clock enable

pub fn spi2en(&self) -> SPI2EN_R

Bit 14 - CPU2 SPI2 clock enable

pub fn rtcapben(&self) -> RTCAPBEN_R

Bit 10 - CPU2 RTC APB clock enable

pub fn lcden(&self) -> LCDEN_R

Bit 9 - CPU2 LCD clock enable

pub fn tim2en(&self) -> TIM2EN_R

Bit 0 - CPU2 TIM2 timer clock enable

impl R<u32, Reg<u32, _C2APB1ENR2>>

pub fn lptim2en(&self) -> LPTIM2EN_R

Bit 5 - CPU2 LPTIM2EN

pub fn lpuart1en(&self) -> LPUART1EN_R

Bit 0 - CPU2 Low power UART 1 clock enable

impl R<u32, Reg<u32, _C2APB2ENR>>

pub fn sai1en(&self) -> SAI1EN_R

Bit 21 - CPU2 SAI1 clock enable

pub fn tim17en(&self) -> TIM17EN_R

Bit 18 - CPU2 TIM17 timer clock enable

pub fn tim16en(&self) -> TIM16EN_R

Bit 17 - CPU2 TIM16 timer clock enable

pub fn usart1en(&self) -> USART1EN_R

Bit 14 - CPU2 USART1clock enable

pub fn spi1en(&self) -> SPI1EN_R

Bit 12 - CPU2 SPI1 clock enable

pub fn tim1en(&self) -> TIM1EN_R

Bit 11 - CPU2 TIM1 timer clock enable

impl R<u32, Reg<u32, _C2APB3ENR>>

pub fn en802(&self) -> EN802_R

Bit 1 - CPU2 802.15.4 interface clock enable

pub fn bleen(&self) -> BLEEN_R

Bit 0 - CPU2 BLE interface clock enable

impl R<u32, Reg<u32, _C2AHB1SMENR>>

pub fn tscsmen(&self) -> TSCSMEN_R

Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&self) -> CRCSMEN_R

Bit 12 - CPU2 CRCSMEN

pub fn sram1smen(&self) -> SRAM1SMEN_R

Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode

pub fn dmamuxsmen(&self) -> DMAMUXSMEN_R

Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes

pub fn dma2smen(&self) -> DMA2SMEN_R

Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&self) -> DMA1SMEN_R

Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes

impl R<u32, Reg<u32, _C2AHB2SMENR>>

pub fn aes1smen(&self) -> AES1SMEN_R

Bit 16 - CPU2 AES1 accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&self) -> ADCFSSMEN_R

Bit 13 - CPU2 ADC clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&self) -> GPIOHSMEN_R

Bit 7 - CPU2 IO port H clocks enable during Sleep and Stop modes

pub fn gpioesmen(&self) -> GPIOESMEN_R

Bit 4 - CPU2 IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&self) -> GPIODSMEN_R

Bit 3 - CPU2 IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&self) -> GPIOCSMEN_R

Bit 2 - CPU2 IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&self) -> GPIOBSMEN_R

Bit 1 - CPU2 IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&self) -> GPIOASMEN_R

Bit 0 - CPU2 IO port A clocks enable during Sleep and Stop modes

impl R<u32, Reg<u32, _C2AHB3SMENR>>

pub fn flashsmen(&self) -> FLASHSMEN_R

Bit 25 - Flash interface clocks enable during CPU2 sleep modes

pub fn sram2smen(&self) -> SRAM2SMEN_R

Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes

pub fn rngsmen(&self) -> RNGSMEN_R

Bit 18 - True RNG clocks enable during CPU2 sleep modes

pub fn aes2smen(&self) -> AES2SMEN_R

Bit 17 - AES2 accelerator clocks enable during CPU2 sleep modes

pub fn pkasmen(&self) -> PKASMEN_R

Bit 16 - PKA accelerator clocks enable during CPU2 sleep modes

impl R<u32, Reg<u32, _C2APB1SMENR1>>

pub fn lptim1smen(&self) -> LPTIM1SMEN_R

Bit 31 - Low power timer 1 clocks enable during CPU2 Sleep mode

pub fn usbsmen(&self) -> USBSMEN_R

Bit 26 - USB FS clocks enable during CPU2 Sleep mode

pub fn crsmen(&self) -> CRSMEN_R

Bit 24 - CRS clocks enable during CPU2 Sleep mode

pub fn i2c3smen(&self) -> I2C3SMEN_R

Bit 23 - I2C3 clocks enable during CPU2 Sleep mode

pub fn i2c1smen(&self) -> I2C1SMEN_R

Bit 21 - I2C1 clocks enable during CPU2 Sleep mode

pub fn spi2smen(&self) -> SPI2SMEN_R

Bit 14 - SPI2 clocks enable during CPU2 Sleep mode

pub fn rtcapbsmen(&self) -> RTCAPBSMEN_R

Bit 10 - RTC APB clocks enable during CPU2 Sleep mode

pub fn lcdsmen(&self) -> LCDSMEN_R

Bit 9 - LCD clocks enable during CPU2 Sleep mode

pub fn tim2smen(&self) -> TIM2SMEN_R

Bit 0 - TIM2 timer clocks enable during CPU2 Sleep mode

impl R<u32, Reg<u32, _C2APB1SMENR2>>

pub fn lptim2smen(&self) -> LPTIM2SMEN_R

Bit 5 - Low power timer 2 clocks enable during CPU2 Sleep mode

pub fn lpuart1smen(&self) -> LPUART1SMEN_R

Bit 0 - Low power UART 1 clocks enable during CPU2 Sleep mode

impl R<u32, Reg<u32, _C2APB2SMENR>>

pub fn sai1smen(&self) -> SAI1SMEN_R

Bit 21 - SAI1 clocks enable during CPU2 Sleep mode

pub fn tim17smen(&self) -> TIM17SMEN_R

Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode

pub fn tim16smen(&self) -> TIM16SMEN_R

Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode

pub fn usart1smen(&self) -> USART1SMEN_R

Bit 14 - USART1clocks enable during CPU2 Sleep mode

pub fn spi1smen(&self) -> SPI1SMEN_R

Bit 12 - SPI1 clocks enable during CPU2 Sleep mode

pub fn tim1smen(&self) -> TIM1SMEN_R

Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode

impl R<u32, Reg<u32, _C2APB3SMENR>>

pub fn smen802(&self) -> SMEN802_R

Bit 1 - 802.15.4 interface clocks enable during CPU2 Sleep modes

pub fn blesmen(&self) -> BLESMEN_R

Bit 0 - BLE interface clocks enable during CPU2 Sleep mode

impl R<u32, Reg<u32, _CR1>>

pub fn lpr(&self) -> LPR_R

Bit 14 - Low-power run

pub fn vos(&self) -> VOS_R

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&self) -> DBP_R

Bit 8 - Disable backup domain write protection

pub fn fpds(&self) -> FPDS_R

Bit 5 - Flash power down mode during LPsSleep for CPU1

pub fn fpdr(&self) -> FPDR_R

Bit 4 - Flash power down mode during LPRun for CPU1

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection for CPU1

impl R<u32, Reg<u32, _CR2>>

pub fn usv(&self) -> USV_R

Bit 10 - VDDUSB USB supply valid

pub fn pvme3(&self) -> PVME3_R

Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V

pub fn pvme1(&self) -> PVME1_R

Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V

pub fn pls(&self) -> PLS_R

Bits 1:3 - Power voltage detector level selection

pub fn pvde(&self) -> PVDE_R

Bit 0 - Power voltage detector enable

impl R<u32, Reg<u32, _CR3>>

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line for CPU1

pub fn ec2h(&self) -> EC2H_R

Bit 14 - Enable CPU2 Hold interrupt for CPU1

pub fn e802a(&self) -> E802A_R

Bit 13 - Enable end of activity interrupt for CPU1

pub fn eblea(&self) -> EBLEA_R

Bit 11 - Enable BLE end of activity interrupt for CPU1

pub fn ecrpe(&self) -> ECRPE_R

Bit 12 - Enable critical radio phase end of activity interrupt for CPU1

pub fn apc(&self) -> APC_R

Bit 10 - Apply pull-up and pull-down configuration

pub fn rrs(&self) -> RRS_R

Bit 9 - SRAM2a retention in Standby mode

pub fn eborhsdfb(&self) -> EBORHSDFB_R

Bit 8 - Enable BORH and Step Down counverter forced in Bypass interrups for CPU1

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable Wakeup pin WKUP5

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup3(&self) -> EWUP3_R

Bit 2 - Enable Wakeup pin WKUP3

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1

impl R<u32, Reg<u32, _CR4>>

pub fn c2boot(&self) -> C2BOOT_R

Bit 15 - BOOT CPU2 after reset or wakeup from Stop or Standby modes

pub fn vbrs(&self) -> VBRS_R

Bit 9 - VBAT battery charging resistor selection

pub fn vbe(&self) -> VBE_R

Bit 8 - VBAT battery charging enable

pub fn wp5(&self) -> WP5_R

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp4(&self) -> WP4_R

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp3(&self) -> WP3_R

Bit 2 - Wakeup pin WKUP3 polarity

pub fn wp2(&self) -> WP2_R

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp1(&self) -> WP1_R

Bit 0 - Wakeup pin WKUP1 polarity

impl R<u32, Reg<u32, _SR1>>

pub fn wufi(&self) -> WUFI_R

Bit 15 - Internal Wakeup interrupt flag

pub fn c2hf(&self) -> C2HF_R

Bit 14 - CPU2 Hold interrupt flag

pub fn af802(&self) -> AF802_R

Bit 13 - 802.15.4 end of activity interrupt flag

pub fn bleaf(&self) -> BLEAF_R

Bit 12 - BLE end of activity interrupt flag

pub fn crpef(&self) -> CRPEF_R

Bit 11 - Enable critical radio phase end of activity interrupt flag

pub fn _802wuf(&self) -> _802WUF_R

Bit 10 - 802.15.4 wakeup interrupt flag

pub fn blewuf(&self) -> BLEWUF_R

Bit 9 - BLE wakeup interrupt flag

pub fn borhf(&self) -> BORHF_R

Bit 8 - BORH interrupt flag

pub fn sdfbf(&self) -> SDFBF_R

Bit 7 - Step Down converter forced in Bypass interrupt flag

pub fn cwuf5(&self) -> CWUF5_R

Bit 4 - Wakeup flag 5

pub fn cwuf4(&self) -> CWUF4_R

Bit 3 - Wakeup flag 4

pub fn cwuf3(&self) -> CWUF3_R

Bit 2 - Wakeup flag 3

pub fn cwuf2(&self) -> CWUF2_R

Bit 1 - Wakeup flag 2

pub fn cwuf1(&self) -> CWUF1_R

Bit 0 - Wakeup flag 1

impl R<u32, Reg<u32, _SR2>>

pub fn pvmo3(&self) -> PVMO3_R

Bit 14 - Peripheral voltage monitoring output: VDDA vs. 1.62 V

pub fn pvmo1(&self) -> PVMO1_R

Bit 12 - Peripheral voltage monitoring output: VDDUSB vs. 1.2 V

pub fn pvdo(&self) -> PVDO_R

Bit 11 - Power voltage detector output

pub fn vosf(&self) -> VOSF_R

Bit 10 - Voltage scaling flag

pub fn reglpf(&self) -> REGLPF_R

Bit 9 - Low-power regulator flag

pub fn reglps(&self) -> REGLPS_R

Bit 8 - Low-power regulator started

pub fn sdsmpsf(&self) -> SDSMPSF_R

Bit 1 - Step Down converter SMPS mode flag

pub fn sdbf(&self) -> SDBF_R

Bit 0 - Step Down converter Bypass mode flag

impl R<u32, Reg<u32, _CR5>>

pub fn sdeb(&self) -> SDEB_R

Bit 15 - Enable Step Down converter SMPS mode enabled

pub fn sdben(&self) -> SDBEN_R

Bit 14 - Enable Step Down converter Bypass mode enabled

pub fn smpscfg(&self) -> SMPSCFG_R

Bit 9 - VOS configuration selection (non user)

pub fn borhc(&self) -> BORHC_R

Bit 8 - BORH configuration selection

pub fn sdsc(&self) -> SDSC_R

Bits 4:6 - Step Down converter supplt startup current selection

pub fn sdvos(&self) -> SDVOS_R

Bits 0:3 - Step Down converter voltage output scaling

impl R<u32, Reg<u32, _PUCRA>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port A pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRA>>

pub fn pd14(&self) -> PD14_R

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port A pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRB>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port B pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRB>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port B pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRC>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port C pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRC>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port C pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRD>>

pub fn pu15(&self) -> PU15_R

Bit 15 - Port D pull-up bit y (y=0..15)

pub fn pu14(&self) -> PU14_R

Bit 14 - Port D pull-up bit y (y=0..15)

pub fn pu13(&self) -> PU13_R

Bit 13 - Port D pull-up bit y (y=0..15)

pub fn pu12(&self) -> PU12_R

Bit 12 - Port D pull-up bit y (y=0..15)

pub fn pu11(&self) -> PU11_R

Bit 11 - Port D pull-up bit y (y=0..15)

pub fn pu10(&self) -> PU10_R

Bit 10 - Port D pull-up bit y (y=0..15)

pub fn pu9(&self) -> PU9_R

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&self) -> PU8_R

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu7(&self) -> PU7_R

Bit 7 - Port D pull-up bit y (y=0..15)

pub fn pu6(&self) -> PU6_R

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&self) -> PU5_R

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&self) -> PU4_R

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port D pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRD>>

pub fn pd15(&self) -> PD15_R

Bit 15 - Port D pull-down bit y (y=0..15)

pub fn pd14(&self) -> PD14_R

Bit 14 - Port D pull-down bit y (y=0..15)

pub fn pd13(&self) -> PD13_R

Bit 13 - Port D pull-down bit y (y=0..15)

pub fn pd12(&self) -> PD12_R

Bit 12 - Port D pull-down bit y (y=0..15)

pub fn pd11(&self) -> PD11_R

Bit 11 - Port D pull-down bit y (y=0..15)

pub fn pd10(&self) -> PD10_R

Bit 10 - Port D pull-down bit y (y=0..15)

pub fn pd9(&self) -> PD9_R

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&self) -> PD8_R

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd7(&self) -> PD7_R

Bit 7 - Port D pull-down bit y (y=0..15)

pub fn pd6(&self) -> PD6_R

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&self) -> PD5_R

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&self) -> PD4_R

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port D pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRE>>

pub fn pu4(&self) -> PU4_R

Bit 4 - Port E pull-up bit y (y=0..15)

pub fn pu3(&self) -> PU3_R

Bit 3 - Port E pull-up bit y (y=0..15)

pub fn pu2(&self) -> PU2_R

Bit 2 - Port E pull-up bit y (y=0..15)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port E pull-up bit y (y=0..15)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port E pull-up bit y (y=0..15)

impl R<u32, Reg<u32, _PDCRE>>

pub fn pd4(&self) -> PD4_R

Bit 4 - Port E pull-down bit y (y=0..15)

pub fn pd3(&self) -> PD3_R

Bit 3 - Port E pull-down bit y (y=0..15)

pub fn pd2(&self) -> PD2_R

Bit 2 - Port E pull-down bit y (y=0..15)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port E pull-down bit y (y=0..15)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port E pull-down bit y (y=0..15)

impl R<u32, Reg<u32, _PUCRH>>

pub fn pu3(&self) -> PU3_R

Bit 3 - Port H pull-up bit y (y=0..1)

pub fn pu1(&self) -> PU1_R

Bit 1 - Port H pull-up bit y (y=0..1)

pub fn pu0(&self) -> PU0_R

Bit 0 - Port H pull-up bit y (y=0..1)

impl R<u32, Reg<u32, _PDCRH>>

pub fn pd3(&self) -> PD3_R

Bit 3 - Port H pull-down bit y (y=0..1)

pub fn pd1(&self) -> PD1_R

Bit 1 - Port H pull-down bit y (y=0..1)

pub fn pd0(&self) -> PD0_R

Bit 0 - Port H pull-down bit y (y=0..1)

impl R<u32, Reg<u32, _C2CR1>>

pub fn _802ewkup(&self) -> _802EWKUP_R

Bit 15 - 802.15.4 external wakeup signal

pub fn bleewkup(&self) -> BLEEWKUP_R

Bit 14 - BLE external wakeup signal

pub fn fpds(&self) -> FPDS_R

Bit 5 - Flash power down mode during LPSleep for CPU2

pub fn fpdr(&self) -> FPDR_R

Bit 4 - Flash power down mode during LPRun for CPU2

pub fn lpms(&self) -> LPMS_R

Bits 0:2 - Low-power mode selection for CPU2

impl R<u32, Reg<u32, _C2CR3>>

pub fn eiwul(&self) -> EIWUL_R

Bit 15 - Enable internal wakeup line for CPU2

pub fn apc(&self) -> APC_R

Bit 12 - Apply pull-up and pull-down configuration for CPU2

pub fn e802wup(&self) -> E802WUP_R

Bit 10 - Enable 802.15.4 host wakeup interrupt for CPU2

pub fn eblewup(&self) -> EBLEWUP_R

Bit 9 - Enable BLE host wakeup interrupt for CPU2

pub fn ewup5(&self) -> EWUP5_R

Bit 4 - Enable Wakeup pin WKUP5 for CPU2

pub fn ewup4(&self) -> EWUP4_R

Bit 3 - Enable Wakeup pin WKUP4 for CPU2

pub fn ewup3(&self) -> EWUP3_R

Bit 2 - Enable Wakeup pin WKUP3 for CPU2

pub fn ewup2(&self) -> EWUP2_R

Bit 1 - Enable Wakeup pin WKUP2 for CPU2

pub fn ewup1(&self) -> EWUP1_R

Bit 0 - Enable Wakeup pin WKUP1 for CPU2

impl R<u32, Reg<u32, _EXTSCR>>

pub fn c2ds(&self) -> C2DS_R

Bit 15 - CPU2 deepsleep mode

pub fn c1ds(&self) -> C1DS_R

Bit 14 - CPU1 deepsleep mode

pub fn crpf(&self) -> CRPF_R

Bit 13 - Critical Radio system phase

pub fn c2stopf(&self) -> C2STOPF_R

Bit 11 - System Stop flag for CPU2

pub fn c2sbf(&self) -> C2SBF_R

Bit 10 - System Standby flag for CPU2

pub fn c1stopf(&self) -> C1STOPF_R

Bit 9 - System Stop flag for CPU1

pub fn c1sbf(&self) -> C1SBF_R

Bit 8 - System Standby flag for CPU1

impl R<u32, Reg<u32, _MEMRMP>>

pub fn mem_mode(&self) -> MEM_MODE_R

Bits 0:2 - Memory mapping selection

impl R<u32, Reg<u32, _CFGR1>>

pub fn fpu_ie(&self) -> FPU_IE_R

Bits 26:31 - Floating Point Unit interrupts enable bits

pub fn i2c3_fmp(&self) -> I2C3_FMP_R

Bit 22 - I2C3 Fast-mode Plus driving capability activation

pub fn i2c1_fmp(&self) -> I2C1_FMP_R

Bit 20 - I2C1 Fast-mode Plus driving capability activation

pub fn i2c_pb9_fmp(&self) -> I2C_PB9_FMP_R

Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9

pub fn i2c_pb8_fmp(&self) -> I2C_PB8_FMP_R

Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8

pub fn i2c_pb7_fmp(&self) -> I2C_PB7_FMP_R

Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7

pub fn i2c_pb6_fmp(&self) -> I2C_PB6_FMP_R

Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6

pub fn boosten(&self) -> BOOSTEN_R

Bit 8 - I/O analog switch voltage booster enable

impl R<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&self) -> EXTI3_R

Bits 12:14 - EXTI 3 configuration bits

pub fn exti2(&self) -> EXTI2_R

Bits 8:10 - EXTI 2 configuration bits

pub fn exti1(&self) -> EXTI1_R

Bits 4:6 - EXTI 1 configuration bits

pub fn exti0(&self) -> EXTI0_R

Bits 0:2 - EXTI 0 configuration bits

impl R<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&self) -> EXTI7_R

Bits 12:14 - EXTI 7 configuration bits

pub fn exti6(&self) -> EXTI6_R

Bits 8:10 - EXTI 6 configuration bits

pub fn exti5(&self) -> EXTI5_R

Bits 4:6 - EXTI 5 configuration bits

pub fn exti4(&self) -> EXTI4_R

Bits 0:2 - EXTI 4 configuration bits

impl R<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&self) -> EXTI11_R

Bits 12:14 - EXTI 11 configuration bits

pub fn exti10(&self) -> EXTI10_R

Bits 8:10 - EXTI 10 configuration bits

pub fn exti9(&self) -> EXTI9_R

Bits 4:6 - EXTI 9 configuration bits

pub fn exti8(&self) -> EXTI8_R

Bits 0:2 - EXTI 8 configuration bits

impl R<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&self) -> EXTI15_R

Bits 12:14 - EXTI15 configuration bits

pub fn exti14(&self) -> EXTI14_R

Bits 8:10 - EXTI14 configuration bits

pub fn exti13(&self) -> EXTI13_R

Bits 4:6 - EXTI13 configuration bits

pub fn exti12(&self) -> EXTI12_R

Bits 0:2 - EXTI12 configuration bits

impl R<u32, Reg<u32, _SCSR>>

pub fn sram2bsy(&self) -> SRAM2BSY_R

Bit 1 - SRAM2 busy by erase operation

pub fn sram2er(&self) -> SRAM2ER_R

Bit 0 - SRAM2 Erase

pub fn c2rfd(&self) -> C2RFD_R

Bit 31 - CPU2 SRAM fetch (execution) disable.

impl R<u32, Reg<u32, _CFGR2>>

pub fn spf(&self) -> SPF_R

Bit 8 - SRAM2 parity error flag

impl R<u32, Reg<u32, _IMR1>>

pub fn tim1im(&self) -> TIM1IM_R

Bit 13 - Peripheral TIM1 interrupt mask to CPU1

pub fn tim16im(&self) -> TIM16IM_R

Bit 14 - Peripheral TIM16 interrupt mask to CPU1

pub fn tim17im(&self) -> TIM17IM_R

Bit 15 - Peripheral TIM17 interrupt mask to CPU1

pub fn exit5im(&self) -> EXIT5IM_R

Bit 21 - Peripheral EXIT5 interrupt mask to CPU1

pub fn exit6im(&self) -> EXIT6IM_R

Bit 22 - Peripheral EXIT6 interrupt mask to CPU1

pub fn exit7im(&self) -> EXIT7IM_R

Bit 23 - Peripheral EXIT7 interrupt mask to CPU1

pub fn exit8im(&self) -> EXIT8IM_R

Bit 24 - Peripheral EXIT8 interrupt mask to CPU1

pub fn exit9im(&self) -> EXIT9IM_R

Bit 25 - Peripheral EXIT9 interrupt mask to CPU1

pub fn exit10im(&self) -> EXIT10IM_R

Bit 26 - Peripheral EXIT10 interrupt mask to CPU1

pub fn exit11im(&self) -> EXIT11IM_R

Bit 27 - Peripheral EXIT11 interrupt mask to CPU1

pub fn exit12im(&self) -> EXIT12IM_R

Bit 28 - Peripheral EXIT12 interrupt mask to CPU1

pub fn exit13im(&self) -> EXIT13IM_R

Bit 29 - Peripheral EXIT13 interrupt mask to CPU1

pub fn exit14im(&self) -> EXIT14IM_R

Bit 30 - Peripheral EXIT14 interrupt mask to CPU1

pub fn exit15im(&self) -> EXIT15IM_R

Bit 31 - Peripheral EXIT15 interrupt mask to CPU1

impl R<u32, Reg<u32, _IMR2>>

pub fn pvm3im(&self) -> PVM3IM_R

Bit 18 - Peripheral PVM3 interrupt mask to CPU1

pub fn pvm1im(&self) -> PVM1IM_R

Bit 16 - Peripheral PVM1 interrupt mask to CPU1

pub fn pvdim(&self) -> PVDIM_R

Bit 20 - Peripheral PVD interrupt mask to CPU1

impl R<u32, Reg<u32, _C2IMR1>>

pub fn rtcstamp(&self) -> RTCSTAMP_R

Bit 0 - Peripheral RTCSTAMP interrupt mask to CPU2

pub fn rtcwkup(&self) -> RTCWKUP_R

Bit 3 - Peripheral RTCWKUP interrupt mask to CPU2

pub fn rtcalarm(&self) -> RTCALARM_R

Bit 4 - Peripheral RTCALARM interrupt mask to CPU2

pub fn rcc(&self) -> RCC_R

Bit 5 - Peripheral RCC interrupt mask to CPU2

pub fn flash(&self) -> FLASH_R

Bit 6 - Peripheral FLASH interrupt mask to CPU2

pub fn pka(&self) -> PKA_R

Bit 8 - Peripheral PKA interrupt mask to CPU2

pub fn rng(&self) -> RNG_R

Bit 9 - Peripheral RNG interrupt mask to CPU2

pub fn aes1(&self) -> AES1_R

Bit 10 - Peripheral AES1 interrupt mask to CPU2

pub fn comp(&self) -> COMP_R

Bit 11 - Peripheral COMP interrupt mask to CPU2

pub fn adc(&self) -> ADC_R

Bit 12 - Peripheral ADC interrupt mask to CPU2

impl R<u32, Reg<u32, _C2IMR2>>

pub fn dma1_ch1_im(&self) -> DMA1_CH1_IM_R

Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2

pub fn dma1_ch2_im(&self) -> DMA1_CH2_IM_R

Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2

pub fn dma1_ch3_im(&self) -> DMA1_CH3_IM_R

Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2

pub fn dma1_ch4_im(&self) -> DMA1_CH4_IM_R

Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2

pub fn dma1_ch5_im(&self) -> DMA1_CH5_IM_R

Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2

pub fn dma1_ch6_im(&self) -> DMA1_CH6_IM_R

Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2

pub fn dma1_ch7_im(&self) -> DMA1_CH7_IM_R

Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2

pub fn dma2_ch1_im(&self) -> DMA2_CH1_IM_R

Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1

pub fn dma2_ch2_im(&self) -> DMA2_CH2_IM_R

Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1

pub fn dma2_ch3_im(&self) -> DMA2_CH3_IM_R

Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1

pub fn dma2_ch4_im(&self) -> DMA2_CH4_IM_R

Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1

pub fn dma2_ch5_im(&self) -> DMA2_CH5_IM_R

Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1

pub fn dma2_ch6_im(&self) -> DMA2_CH6_IM_R

Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1

pub fn dma2_ch7_im(&self) -> DMA2_CH7_IM_R

Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1

pub fn dmam_ux1_im(&self) -> DMAM_UX1_IM_R

Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1

pub fn pvm1im(&self) -> PVM1IM_R

Bit 16 - Peripheral PVM1IM interrupt mask to CPU1

pub fn pvm3im(&self) -> PVM3IM_R

Bit 18 - Peripheral PVM3IM interrupt mask to CPU1

pub fn pvdim(&self) -> PVDIM_R

Bit 20 - Peripheral PVDIM interrupt mask to CPU1

pub fn tscim(&self) -> TSCIM_R

Bit 21 - Peripheral TSCIM interrupt mask to CPU1

pub fn lcdim(&self) -> LCDIM_R

Bit 22 - Peripheral LCDIM interrupt mask to CPU1

impl R<u32, Reg<u32, _SIPCR>>

pub fn saes1(&self) -> SAES1_R

Bit 0 - Enable AES1 KEY[7:0] security.

pub fn saes2(&self) -> SAES2_R

Bit 1 - Enable AES2 security.

pub fn spka(&self) -> SPKA_R

Bit 2 - Enable PKA security

pub fn srng(&self) -> SRNG_R

Bit 3 - Enable True RNG security

impl R<u32, Reg<u32, _CR>>

pub fn rngen(&self) -> RNGEN_R

Bit 2 - Random number generator enable

pub fn ie(&self) -> IE_R

Bit 3 - Interrupt enable

pub fn byp(&self) -> BYP_R

Bit 6 - Bypass mode enable

impl R<u32, Reg<u32, _SR>>

pub fn seis(&self) -> SEIS_R

Bit 6 - Seed error interrupt status

pub fn ceis(&self) -> CEIS_R

Bit 5 - Clock error interrupt status

pub fn secs(&self) -> SECS_R

Bit 2 - Seed error current status

pub fn cecs(&self) -> CECS_R

Bit 1 - Clock error current status

pub fn drdy(&self) -> DRDY_R

Bit 0 - Data ready

impl R<u32, Reg<u32, _DR>>

pub fn rndata(&self) -> RNDATA_R

Bits 0:31 - Random data

impl R<u32, Reg<u32, _CR>>

pub fn npblb(&self) -> NPBLB_R

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&self) -> KEYSIZE_R

Bit 18 - Key size selection

pub fn chmod2(&self) -> CHMOD2_R

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&self) -> GCMPH_R

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&self) -> DMAOUTEN_R

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&self) -> DMAINEN_R

Bit 11 - Enable DMA management of data input phase

pub fn errie(&self) -> ERRIE_R

Bit 10 - Error interrupt enable

pub fn ccfie(&self) -> CCFIE_R

Bit 9 - CCF flag interrupt enable

pub fn errc(&self) -> ERRC_R

Bit 8 - Error clear

pub fn ccfc(&self) -> CCFC_R

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&self) -> CHMOD10_R

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&self) -> MODE_R

Bits 3:4 - AES operating mode

pub fn datatype(&self) -> DATATYPE_R

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&self) -> EN_R

Bit 0 - AES enable

impl R<u32, Reg<u32, _SR>>

pub fn busy(&self) -> BUSY_R

Bit 3 - Busy flag

pub fn wrerr(&self) -> WRERR_R

Bit 2 - Write error flag

pub fn rderr(&self) -> RDERR_R

Bit 1 - Read error flag

pub fn ccf(&self) -> CCF_R

Bit 0 - Computation complete flag

impl R<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&self) -> AES_DINR_R

Bits 0:31 - Data Input Register

impl R<u32, Reg<u32, _DOUTR>>

pub fn aes_doutr(&self) -> AES_DOUTR_R

Bits 0:31 - Data output register

impl R<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&self) -> AES_KEYR0_R

Bits 0:31 - Data Output Register (LSB key [31:0])

impl R<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&self) -> AES_KEYR1_R

Bits 0:31 - AES key register (key [63:32])

impl R<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&self) -> AES_KEYR2_R

Bits 0:31 - AES key register (key [95:64])

impl R<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&self) -> AES_KEYR3_R

Bits 0:31 - AES key register (MSB key [127:96])

impl R<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&self) -> AES_IVR0_R

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl R<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&self) -> AES_IVR1_R

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl R<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&self) -> AES_IVR2_R

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl R<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&self) -> AES_IVR3_R

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl R<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&self) -> AES_KEYR4_R

Bits 0:31 - AES key register (MSB key [159:128])

impl R<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&self) -> AES_KEYR5_R

Bits 0:31 - AES key register (MSB key [191:160])

impl R<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&self) -> AES_KEYR6_R

Bits 0:31 - AES key register (MSB key [223:192])

impl R<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&self) -> AES_KEYR7_R

Bits 0:31 - AES key register (MSB key [255:224])

impl R<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&self) -> AES_SUSP0R_R

Bits 0:31 - AES suspend register 0

impl R<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&self) -> AES_SUSP1R_R

Bits 0:31 - AES suspend register 1

impl R<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&self) -> AES_SUSP2R_R

Bits 0:31 - AES suspend register 2

impl R<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&self) -> AES_SUSP3R_R

Bits 0:31 - AES suspend register 3

impl R<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&self) -> AES_SUSP4R_R

Bits 0:31 - AES suspend register 4

impl R<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&self) -> AES_SUSP5R_R

Bits 0:31 - AES suspend register 5

impl R<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&self) -> AES_SUSP6R_R

Bits 0:31 - AES suspend register 6

impl R<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&self) -> AES_SUSP7R_R

Bits 0:31 - AES suspend register 7

impl R<u32, Reg<u32, _HWCFR>>

pub fn cfg4(&self) -> CFG4_R

Bits 12:15 - HW Generic 4

pub fn cfg3(&self) -> CFG3_R

Bits 8:11 - HW Generic 3

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - HW Generic 2

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - HW Generic 1

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification code

impl R<u32, Reg<u32, _SIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Size Identification code

impl R<u32, Reg<u32, _CR>>

pub fn npblb(&self) -> NPBLB_R

Bits 20:23 - Number of padding bytes in last block of payload

pub fn keysize(&self) -> KEYSIZE_R

Bit 18 - Key size selection

pub fn chmod2(&self) -> CHMOD2_R

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&self) -> GCMPH_R

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&self) -> DMAOUTEN_R

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&self) -> DMAINEN_R

Bit 11 - Enable DMA management of data input phase

pub fn errie(&self) -> ERRIE_R

Bit 10 - Error interrupt enable

pub fn ccfie(&self) -> CCFIE_R

Bit 9 - CCF flag interrupt enable

pub fn errc(&self) -> ERRC_R

Bit 8 - Error clear

pub fn ccfc(&self) -> CCFC_R

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&self) -> CHMOD10_R

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&self) -> MODE_R

Bits 3:4 - AES operating mode

pub fn datatype(&self) -> DATATYPE_R

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&self) -> EN_R

Bit 0 - AES enable

impl R<u32, Reg<u32, _SR>>

pub fn busy(&self) -> BUSY_R

Bit 3 - Busy flag

pub fn wrerr(&self) -> WRERR_R

Bit 2 - Write error flag

pub fn rderr(&self) -> RDERR_R

Bit 1 - Read error flag

pub fn ccf(&self) -> CCF_R

Bit 0 - Computation complete flag

impl R<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&self) -> AES_DINR_R

Bits 0:31 - Data Input Register

impl R<u32, Reg<u32, _DOUTR>>

pub fn aes_doutr(&self) -> AES_DOUTR_R

Bits 0:31 - Data output register

impl R<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&self) -> AES_KEYR0_R

Bits 0:31 - Data Output Register (LSB key [31:0])

impl R<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&self) -> AES_KEYR1_R

Bits 0:31 - AES key register (key [63:32])

impl R<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&self) -> AES_KEYR2_R

Bits 0:31 - AES key register (key [95:64])

impl R<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&self) -> AES_KEYR3_R

Bits 0:31 - AES key register (MSB key [127:96])

impl R<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&self) -> AES_IVR0_R

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl R<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&self) -> AES_IVR1_R

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl R<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&self) -> AES_IVR2_R

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl R<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&self) -> AES_IVR3_R

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl R<u32, Reg<u32, _KEYR4>>

pub fn aes_keyr4(&self) -> AES_KEYR4_R

Bits 0:31 - AES key register (MSB key [159:128])

impl R<u32, Reg<u32, _KEYR5>>

pub fn aes_keyr5(&self) -> AES_KEYR5_R

Bits 0:31 - AES key register (MSB key [191:160])

impl R<u32, Reg<u32, _KEYR6>>

pub fn aes_keyr6(&self) -> AES_KEYR6_R

Bits 0:31 - AES key register (MSB key [223:192])

impl R<u32, Reg<u32, _KEYR7>>

pub fn aes_keyr7(&self) -> AES_KEYR7_R

Bits 0:31 - AES key register (MSB key [255:224])

impl R<u32, Reg<u32, _SUSP0R>>

pub fn aes_susp0r(&self) -> AES_SUSP0R_R

Bits 0:31 - AES suspend register 0

impl R<u32, Reg<u32, _SUSP1R>>

pub fn aes_susp1r(&self) -> AES_SUSP1R_R

Bits 0:31 - AES suspend register 1

impl R<u32, Reg<u32, _SUSP2R>>

pub fn aes_susp2r(&self) -> AES_SUSP2R_R

Bits 0:31 - AES suspend register 2

impl R<u32, Reg<u32, _SUSP3R>>

pub fn aes_susp3r(&self) -> AES_SUSP3R_R

Bits 0:31 - AES suspend register 3

impl R<u32, Reg<u32, _SUSP4R>>

pub fn aes_susp4r(&self) -> AES_SUSP4R_R

Bits 0:31 - AES suspend register 4

impl R<u32, Reg<u32, _SUSP5R>>

pub fn aes_susp5r(&self) -> AES_SUSP5R_R

Bits 0:31 - AES suspend register 5

impl R<u32, Reg<u32, _SUSP6R>>

pub fn aes_susp6r(&self) -> AES_SUSP6R_R

Bits 0:31 - AES suspend register 6

impl R<u32, Reg<u32, _SUSP7R>>

pub fn aes_susp7r(&self) -> AES_SUSP7R_R

Bits 0:31 - AES suspend register 7

impl R<u32, Reg<u32, _HWCFR>>

pub fn cfg4(&self) -> CFG4_R

Bits 12:15 - HW Generic 4

pub fn cfg3(&self) -> CFG3_R

Bits 8:11 - HW Generic 3

pub fn cfg2(&self) -> CFG2_R

Bits 4:7 - HW Generic 2

pub fn cfg1(&self) -> CFG1_R

Bits 0:3 - HW Generic 1

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification code

impl R<u32, Reg<u32, _SIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Size Identification code

impl R<u32, Reg<u32, _R0>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R1>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R2>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R3>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R4>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R5>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R6>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R7>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R8>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R9>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R10>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R11>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R12>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R13>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R14>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R15>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R16>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R17>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R18>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R19>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R20>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R21>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R22>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R23>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R24>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R25>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R26>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R27>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R28>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R29>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R30>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _R31>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR0>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR1>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR2>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR3>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR4>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR5>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR6>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR7>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR8>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR9>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR10>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR11>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR12>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR13>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR14>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR15>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR16>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR17>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR18>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR19>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR20>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR21>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR22>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR23>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR24>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR25>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR26>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR27>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR28>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR29>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR30>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _RLR31>>

pub fn lock(&self) -> LOCK_R

Bit 31 - lock indication

pub fn coreid(&self) -> COREID_R

Bits 8:11 - Semaphore CoreID

pub fn procid(&self) -> PROCID_R

Bits 0:7 - Semaphore ProcessID

impl R<u32, Reg<u32, _CR>>

pub fn key(&self) -> KEY_R

Bits 16:31 - Semaphore clear Key

pub fn coreid(&self) -> COREID_R

Bits 8:11 - CoreID of semaphore to be cleared

impl R<u32, Reg<u32, _KEYR>>

pub fn key(&self) -> KEY_R

Bits 16:31 - Semaphore Clear Key

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn masterid4(&self) -> MASTERID4_R

Bits 12:15 - Hardware Configuration valid bus masters ID4

pub fn masterid3(&self) -> MASTERID3_R

Bits 8:11 - Hardware Configuration valid bus masters ID3

pub fn masterid2(&self) -> MASTERID2_R

Bits 4:7 - Hardware Configuration valid bus masters ID2

pub fn masterid1(&self) -> MASTERID1_R

Bits 0:3 - Hardware Configuration valid bus masters ID1

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn nbint(&self) -> NBINT_R

Bits 8:11 - Hardware Configuration number of interrupts supported number of master IDs

pub fn nbsem(&self) -> NBSEM_R

Bits 0:7 - Hardware Configuration number of semaphores

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification Code

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification Code

impl R<u32, Reg<u32, _C1IER>>

pub fn isem(&self) -> ISEM_R

Bits 0:31 - CPU(n) semaphore m enable bit

impl R<u32, Reg<u32, _C1ICR>>

pub fn iscm(&self) -> ISCM_R

Bits 0:31 - CPU(n) semaphore m clear bit

impl R<u32, Reg<u32, _C1ISR>>

pub fn isfm(&self) -> ISFM_R

Bits 0:31 - CPU(n) semaphore m status bit before enable (mask)

impl R<u32, Reg<u32, _C1MISR>>

pub fn misfm(&self) -> MISFM_R

Bits 0:31 - masked CPU(n) semaphore m status bit after enable (mask).

impl R<u32, Reg<u32, _C2IER>>

pub fn isem(&self) -> ISEM_R

Bits 0:31 - CPU(2) semaphore m enable bit.

impl R<u32, Reg<u32, _C2ICR>>

pub fn iscm(&self) -> ISCM_R

Bits 0:31 - CPU(2) semaphore m clear bit

impl R<u32, Reg<u32, _C2ISR>>

pub fn isfm(&self) -> ISFM_R

Bits 0:31 - CPU(2) semaphore m status bit before enable (mask).

impl R<u32, Reg<u32, _C2MISR>>

pub fn misfm(&self) -> MISFM_R

Bits 0:31 - masked CPU(2) semaphore m status bit after enable (mask).

impl R<u32, Reg<u32, _ISR>>

pub fn jqovf(&self) -> JQOVF_R

Bit 10 - ADC group injected contexts queue overflow flag

pub fn awd3(&self) -> AWD3_R

Bit 9 - ADC analog watchdog 3 flag

pub fn awd2(&self) -> AWD2_R

Bit 8 - ADC analog watchdog 2 flag

pub fn awd1(&self) -> AWD1_R

Bit 7 - ADC analog watchdog 1 flag

pub fn jeos(&self) -> JEOS_R

Bit 6 - ADC group injected end of sequence conversions flag

pub fn jeoc(&self) -> JEOC_R

Bit 5 - ADC group injected end of unitary conversion flag

pub fn ovr(&self) -> OVR_R

Bit 4 - ADC group regular overrun flag

pub fn eos(&self) -> EOS_R

Bit 3 - ADC group regular end of sequence conversions flag

pub fn eoc(&self) -> EOC_R

Bit 2 - ADC group regular end of unitary conversion flag

pub fn eosmp(&self) -> EOSMP_R

Bit 1 - ADC group regular end of sampling flag

pub fn adrdy(&self) -> ADRDY_R

Bit 0 - ADC ready flag

impl R<u32, Reg<u32, _IER>>

pub fn jqovfie(&self) -> JQOVFIE_R

Bit 10 - ADC group injected contexts queue overflow interrupt

pub fn awd3ie(&self) -> AWD3IE_R

Bit 9 - ADC analog watchdog 3 interrupt

pub fn awd2ie(&self) -> AWD2IE_R

Bit 8 - ADC analog watchdog 2 interrupt

pub fn awd1ie(&self) -> AWD1IE_R

Bit 7 - ADC analog watchdog 1 interrupt

pub fn jeosie(&self) -> JEOSIE_R

Bit 6 - ADC group injected end of sequence conversions interrupt

pub fn jeocie(&self) -> JEOCIE_R

Bit 5 - ADC group injected end of unitary conversion interrupt

pub fn ovrie(&self) -> OVRIE_R

Bit 4 - ADC group regular overrun interrupt

pub fn eosie(&self) -> EOSIE_R

Bit 3 - ADC group regular end of sequence conversions interrupt

pub fn eocie(&self) -> EOCIE_R

Bit 2 - ADC group regular end of unitary conversion interrupt

pub fn eosmpie(&self) -> EOSMPIE_R

Bit 1 - ADC group regular end of sampling interrupt

pub fn adrdyie(&self) -> ADRDYIE_R

Bit 0 - ADC ready interrupt

impl R<u32, Reg<u32, _CR>>

pub fn adcal(&self) -> ADCAL_R

Bit 31 - ADC calibration

pub fn adcaldif(&self) -> ADCALDIF_R

Bit 30 - ADC differential mode for calibration

pub fn deeppwd(&self) -> DEEPPWD_R

Bit 29 - ADC deep power down enable

pub fn advregen(&self) -> ADVREGEN_R

Bit 28 - ADC voltage regulator enable

pub fn jadstp(&self) -> JADSTP_R

Bit 5 - ADC group injected conversion stop

pub fn adstp(&self) -> ADSTP_R

Bit 4 - ADC group regular conversion stop

pub fn jadstart(&self) -> JADSTART_R

Bit 3 - ADC group injected conversion start

pub fn adstart(&self) -> ADSTART_R

Bit 2 - ADC group regular conversion start

pub fn addis(&self) -> ADDIS_R

Bit 1 - ADC disable

pub fn aden(&self) -> ADEN_R

Bit 0 - ADC enable

impl R<u32, Reg<u32, _CFGR>>

pub fn jqdis(&self) -> JQDIS_R

Bit 31 - ADC group injected contexts queue disable

pub fn awdch1ch(&self) -> AWDCH1CH_R

Bits 26:30 - ADC analog watchdog 1 monitored channel selection

pub fn jauto(&self) -> JAUTO_R

Bit 25 - ADC group injected automatic trigger mode

pub fn jawd1en(&self) -> JAWD1EN_R

Bit 24 - ADC analog watchdog 1 enable on scope ADC group injected

pub fn awd1en(&self) -> AWD1EN_R

Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular

pub fn awd1sgl(&self) -> AWD1SGL_R

Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels

pub fn jqm(&self) -> JQM_R

Bit 21 - ADC group injected contexts queue mode

pub fn jdiscen(&self) -> JDISCEN_R

Bit 20 - ADC group injected sequencer discontinuous mode

pub fn discnum(&self) -> DISCNUM_R

Bits 17:19 - ADC group regular sequencer discontinuous number of ranks

pub fn discen(&self) -> DISCEN_R

Bit 16 - ADC group regular sequencer discontinuous mode

pub fn autdly(&self) -> AUTDLY_R

Bit 14 - ADC low power auto wait

pub fn cont(&self) -> CONT_R

Bit 13 - ADC group regular continuous conversion mode

pub fn ovrmod(&self) -> OVRMOD_R

Bit 12 - ADC group regular overrun configuration

pub fn exten(&self) -> EXTEN_R

Bits 10:11 - ADC group regular external trigger polarity

pub fn extsel(&self) -> EXTSEL_R

Bits 6:9 - ADC group regular external trigger source

pub fn align(&self) -> ALIGN_R

Bit 5 - ADC data alignement

pub fn res(&self) -> RES_R

Bits 3:4 - ADC data resolution

pub fn dmacfg(&self) -> DMACFG_R

Bit 1 - ADC DMA transfer configuration

pub fn dmaen(&self) -> DMAEN_R

Bit 0 - ADC DMA transfer enable

impl R<u32, Reg<u32, _CFGR2>>

pub fn rovsm(&self) -> ROVSM_R

Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected

pub fn tovs(&self) -> TOVS_R

Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular

pub fn ovss(&self) -> OVSS_R

Bits 5:8 - ADC oversampling shift

pub fn ovsr(&self) -> OVSR_R

Bits 2:4 - ADC oversampling ratio

pub fn jovse(&self) -> JOVSE_R

Bit 1 - ADC oversampler enable on scope ADC group injected

pub fn rovse(&self) -> ROVSE_R

Bit 0 - ADC oversampler enable on scope ADC group regular

impl R<u32, Reg<u32, _SMPR1>>

pub fn smp9(&self) -> SMP9_R

Bits 27:29 - ADC channel 9 sampling time selection

pub fn smp8(&self) -> SMP8_R

Bits 24:26 - ADC channel 8 sampling time selection

pub fn smp7(&self) -> SMP7_R

Bits 21:23 - ADC channel 7 sampling time selection

pub fn smp6(&self) -> SMP6_R

Bits 18:20 - ADC channel 6 sampling time selection

pub fn smp5(&self) -> SMP5_R

Bits 15:17 - ADC channel 5 sampling time selection

pub fn smp4(&self) -> SMP4_R

Bits 12:14 - ADC channel 4 sampling time selection

pub fn smp3(&self) -> SMP3_R

Bits 9:11 - ADC channel 3 sampling time selection

pub fn smp2(&self) -> SMP2_R

Bits 6:8 - ADC channel 2 sampling time selection

pub fn smp1(&self) -> SMP1_R

Bits 3:5 - ADC channel 1 sampling time selection

impl R<u32, Reg<u32, _SMPR2>>

pub fn smp18(&self) -> SMP18_R

Bits 24:26 - ADC channel 18 sampling time selection

pub fn smp17(&self) -> SMP17_R

Bits 21:23 - ADC channel 17 sampling time selection

pub fn smp16(&self) -> SMP16_R

Bits 18:20 - ADC channel 16 sampling time selection

pub fn smp15(&self) -> SMP15_R

Bits 15:17 - ADC channel 15 sampling time selection

pub fn smp14(&self) -> SMP14_R

Bits 12:14 - ADC channel 14 sampling time selection

pub fn smp13(&self) -> SMP13_R

Bits 9:11 - ADC channel 13 sampling time selection

pub fn smp12(&self) -> SMP12_R

Bits 6:8 - ADC channel 12 sampling time selection

pub fn smp11(&self) -> SMP11_R

Bits 3:5 - ADC channel 11 sampling time selection

pub fn smp10(&self) -> SMP10_R

Bits 0:2 - ADC channel 10 sampling time selection

impl R<u32, Reg<u32, _TR1>>

pub fn ht1(&self) -> HT1_R

Bits 16:27 - ADC analog watchdog 1 threshold high

pub fn lt1(&self) -> LT1_R

Bits 0:11 - ADC analog watchdog 1 threshold low

impl R<u32, Reg<u32, _TR2>>

pub fn ht2(&self) -> HT2_R

Bits 16:23 - ADC analog watchdog 2 threshold high

pub fn lt2(&self) -> LT2_R

Bits 0:7 - ADC analog watchdog 2 threshold low

impl R<u32, Reg<u32, _TR3>>

pub fn ht3(&self) -> HT3_R

Bits 16:23 - ADC analog watchdog 3 threshold high

pub fn lt3(&self) -> LT3_R

Bits 0:7 - ADC analog watchdog 3 threshold low

impl R<u32, Reg<u32, _SQR1>>

pub fn sq4(&self) -> SQ4_R

Bits 24:28 - ADC group regular sequencer rank 4

pub fn sq3(&self) -> SQ3_R

Bits 18:22 - ADC group regular sequencer rank 3

pub fn sq2(&self) -> SQ2_R

Bits 12:16 - ADC group regular sequencer rank 2

pub fn sq1(&self) -> SQ1_R

Bits 6:10 - ADC group regular sequencer rank 1

pub fn l(&self) -> L_R

Bits 0:3 - Regular channel sequence length

impl R<u32, Reg<u32, _SQR2>>

pub fn sq9(&self) -> SQ9_R

Bits 24:28 - ADC group regular sequencer rank 9

pub fn sq8(&self) -> SQ8_R

Bits 18:22 - ADC group regular sequencer rank 8

pub fn sq7(&self) -> SQ7_R

Bits 12:16 - ADC group regular sequencer rank 7

pub fn sq6(&self) -> SQ6_R

Bits 6:10 - ADC group regular sequencer rank 6

pub fn sq5(&self) -> SQ5_R

Bits 0:4 - ADC group regular sequencer rank 5

impl R<u32, Reg<u32, _SQR3>>

pub fn sq14(&self) -> SQ14_R

Bits 24:28 - ADC group regular sequencer rank 14

pub fn sq13(&self) -> SQ13_R

Bits 18:22 - ADC group regular sequencer rank 13

pub fn sq12(&self) -> SQ12_R

Bits 12:16 - ADC group regular sequencer rank 12

pub fn sq11(&self) -> SQ11_R

Bits 6:10 - ADC group regular sequencer rank 11

pub fn sq10(&self) -> SQ10_R

Bits 0:4 - ADC group regular sequencer rank 10

impl R<u32, Reg<u32, _SQR4>>

pub fn sq16(&self) -> SQ16_R

Bits 6:10 - ADC group regular sequencer rank 16

pub fn sq15(&self) -> SQ15_R

Bits 0:4 - ADC group regular sequencer rank 15

impl R<u32, Reg<u32, _DR>>

pub fn rdata_0_6(&self) -> RDATA_0_6_R

Bits 0:5 - Regular Data converted 0_6

pub fn rdata_7_15(&self) -> RDATA_7_15_R

Bits 7:15 - 15

impl R<u32, Reg<u32, _JSQR>>

pub fn jsq4(&self) -> JSQ4_R

Bits 26:30 - ADC group injected sequencer rank 4

pub fn jsq3(&self) -> JSQ3_R

Bits 20:24 - ADC group injected sequencer rank 3

pub fn jsq2(&self) -> JSQ2_R

Bits 14:18 - ADC group injected sequencer rank 2

pub fn jsq1(&self) -> JSQ1_R

Bits 8:12 - ADC group injected sequencer rank 1

pub fn jexten(&self) -> JEXTEN_R

Bits 6:7 - ADC group injected external trigger polarity

pub fn jextsel(&self) -> JEXTSEL_R

Bits 2:5 - ADC group injected external trigger source

pub fn jl(&self) -> JL_R

Bits 0:1 - ADC group injected sequencer scan length

impl R<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&self) -> OFFSET1_EN_R

Bit 31 - ADC offset number 1 enable

pub fn offset1_ch(&self) -> OFFSET1_CH_R

Bits 26:30 - ADC offset number 1 channel selection

pub fn offset1(&self) -> OFFSET1_R

Bits 0:11 - ADC offset number 1 offset level

impl R<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&self) -> OFFSET2_EN_R

Bit 31 - ADC offset number 2 enable

pub fn offset2_ch(&self) -> OFFSET2_CH_R

Bits 26:30 - ADC offset number 2 channel selection

pub fn offset2(&self) -> OFFSET2_R

Bits 0:11 - ADC offset number 2 offset level

impl R<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&self) -> OFFSET3_EN_R

Bit 31 - ADC offset number 3 enable

pub fn offset3_ch(&self) -> OFFSET3_CH_R

Bits 26:30 - ADC offset number 3 channel selection

pub fn offset3(&self) -> OFFSET3_R

Bits 0:11 - ADC offset number 3 offset level

impl R<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&self) -> OFFSET4_EN_R

Bit 31 - ADC offset number 4 enable

pub fn offset4_ch(&self) -> OFFSET4_CH_R

Bits 26:30 - ADC offset number 4 channel selection

pub fn offset4(&self) -> OFFSET4_R

Bits 0:11 - ADC offset number 4 offset level

impl R<u32, Reg<u32, _JDR1>>

pub fn jdata1(&self) -> JDATA1_R

Bits 0:15 - ADC group injected sequencer rank 1 conversion data

impl R<u32, Reg<u32, _JDR2>>

pub fn jdata2(&self) -> JDATA2_R

Bits 0:15 - ADC group injected sequencer rank 2 conversion data

impl R<u32, Reg<u32, _JDR3>>

pub fn jdata3(&self) -> JDATA3_R

Bits 0:15 - ADC group injected sequencer rank 3 conversion data

impl R<u32, Reg<u32, _JDR4>>

pub fn jdata4(&self) -> JDATA4_R

Bits 0:15 - ADC group injected sequencer rank 4 conversion data

impl R<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&self) -> AWD2CH_R

Bits 0:18 - ADC analog watchdog 2 monitored channel selection

impl R<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&self) -> AWD3CH_R

Bits 0:18 - ADC analog watchdog 3 monitored channel selection

impl R<u32, Reg<u32, _DIFSEL>>

pub fn difsel_0(&self) -> DIFSEL_0_R

Bit 0 - ADC channel differential or single-ended mode for channel 0

pub fn difsel_1_15(&self) -> DIFSEL_1_15_R

Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15

pub fn difsel_16_18(&self) -> DIFSEL_16_18_R

Bits 16:18 - ADC channel differential or single-ended mode for channels 18 to 16

impl R<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&self) -> CALFACT_D_R

Bits 16:22 - ADC calibration factor in differential mode

pub fn calfact_s(&self) -> CALFACT_S_R

Bits 0:6 - ADC calibration factor in single-ended mode

impl R<u32, Reg<u32, _CCR>>

pub fn vbaten(&self) -> VBATEN_R

Bit 24 - VBAT enable

pub fn tsen(&self) -> TSEN_R

Bit 23 - Temperature sensor enable

pub fn vrefen(&self) -> VREFEN_R

Bit 22 - VREFEN

pub fn presc(&self) -> PRESC_R

Bits 18:21 - ADC prescaler

pub fn ckmode(&self) -> CKMODE_R

Bits 16:17 - ADC clock mode

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder15(&self) -> MODER15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&self) -> MODER14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&self) -> MODER13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&self) -> MODER12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&self) -> MODER11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&self) -> MODER10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&self) -> MODER9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&self) -> MODER8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&self) -> MODER7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&self) -> MODER6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&self) -> MODER5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot15(&self) -> OT15_R

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&self) -> OT14_R

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&self) -> OT13_R

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&self) -> OT12_R

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&self) -> OT11_R

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&self) -> OT10_R

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&self) -> OT9_R

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&self) -> OT8_R

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&self) -> OT7_R

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&self) -> OT6_R

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&self) -> OT5_R

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&self) -> OSPEEDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&self) -> OSPEEDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&self) -> OSPEEDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&self) -> OSPEEDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&self) -> OSPEEDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&self) -> OSPEEDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&self) -> OSPEEDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&self) -> OSPEEDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&self) -> OSPEEDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&self) -> OSPEEDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&self) -> OSPEEDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&self) -> PUPDR15_R

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&self) -> PUPDR14_R

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&self) -> PUPDR13_R

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&self) -> PUPDR12_R

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&self) -> PUPDR11_R

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&self) -> PUPDR10_R

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&self) -> PUPDR9_R

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&self) -> PUPDR8_R

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&self) -> PUPDR7_R

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&self) -> PUPDR6_R

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&self) -> PUPDR5_R

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr15(&self) -> IDR15_R

Bit 15 - Port input data (y = 0..15)

pub fn idr14(&self) -> IDR14_R

Bit 14 - Port input data (y = 0..15)

pub fn idr13(&self) -> IDR13_R

Bit 13 - Port input data (y = 0..15)

pub fn idr12(&self) -> IDR12_R

Bit 12 - Port input data (y = 0..15)

pub fn idr11(&self) -> IDR11_R

Bit 11 - Port input data (y = 0..15)

pub fn idr10(&self) -> IDR10_R

Bit 10 - Port input data (y = 0..15)

pub fn idr9(&self) -> IDR9_R

Bit 9 - Port input data (y = 0..15)

pub fn idr8(&self) -> IDR8_R

Bit 8 - Port input data (y = 0..15)

pub fn idr7(&self) -> IDR7_R

Bit 7 - Port input data (y = 0..15)

pub fn idr6(&self) -> IDR6_R

Bit 6 - Port input data (y = 0..15)

pub fn idr5(&self) -> IDR5_R

Bit 5 - Port input data (y = 0..15)

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr15(&self) -> ODR15_R

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&self) -> ODR14_R

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&self) -> ODR13_R

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&self) -> ODR12_R

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&self) -> ODR11_R

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&self) -> ODR10_R

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&self) -> ODR9_R

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&self) -> ODR8_R

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&self) -> ODR7_R

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&self) -> ODR6_R

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&self) -> ODR5_R

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&self) -> LCK15_R

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&self) -> LCK14_R

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&self) -> LCK13_R

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&self) -> LCK12_R

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&self) -> LCK11_R

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&self) -> LCK10_R

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&self) -> LCK9_R

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&self) -> LCK8_R

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&self) -> LCK7_R

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&self) -> LCK6_R

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&self) -> LCK5_R

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel7(&self) -> AFSEL7_R

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel6(&self) -> AFSEL6_R

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel5(&self) -> AFSEL5_R

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder4(&self) -> MODER4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&self) -> MODER2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot4(&self) -> OT4_R

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&self) -> OT2_R

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr4(&self) -> OSPEEDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&self) -> OSPEEDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr4(&self) -> PUPDR4_R

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&self) -> PUPDR2_R

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr4(&self) -> IDR4_R

Bit 4 - Port input data (y = 0..15)

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr2(&self) -> IDR2_R

Bit 2 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr4(&self) -> ODR4_R

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&self) -> ODR2_R

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck4(&self) -> LCK4_R

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&self) -> LCK2_R

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel4(&self) -> AFSEL4_R

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel2(&self) -> AFSEL2_R

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _MODER>>

pub fn moder3(&self) -> MODER3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder1(&self) -> MODER1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&self) -> MODER0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OTYPER>>

pub fn ot3(&self) -> OT3_R

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot1(&self) -> OT1_R

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&self) -> OT0_R

Bit 0 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr3(&self) -> OSPEEDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&self) -> OSPEEDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&self) -> OSPEEDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _PUPDR>>

pub fn pupdr3(&self) -> PUPDR3_R

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&self) -> PUPDR1_R

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&self) -> PUPDR0_R

Bits 0:1 - Port x configuration bits (y = 0..15)

impl R<u32, Reg<u32, _IDR>>

pub fn idr3(&self) -> IDR3_R

Bit 3 - Port input data (y = 0..15)

pub fn idr1(&self) -> IDR1_R

Bit 1 - Port input data (y = 0..15)

pub fn idr0(&self) -> IDR0_R

Bit 0 - Port input data (y = 0..15)

impl R<u32, Reg<u32, _ODR>>

pub fn odr3(&self) -> ODR3_R

Bit 3 - Port output data (y = 0..15)

pub fn odr1(&self) -> ODR1_R

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&self) -> ODR0_R

Bit 0 - Port output data (y = 0..15)

impl R<u32, Reg<u32, _LCKR>>

pub fn lckk(&self) -> LCKK_R

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck3(&self) -> LCK3_R

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck1(&self) -> LCK1_R

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&self) -> LCK0_R

Bit 0 - Port x lock bit y (y= 0..15)

impl R<u32, Reg<u32, _AFRL>>

pub fn afsel3(&self) -> AFSEL3_R

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel1(&self) -> AFSEL1_R

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afsel0(&self) -> AFSEL0_R

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl R<u32, Reg<u32, _AFRH>>

pub fn afsel15(&self) -> AFSEL15_R

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel14(&self) -> AFSEL14_R

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel13(&self) -> AFSEL13_R

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel12(&self) -> AFSEL12_R

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel11(&self) -> AFSEL11_R

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel10(&self) -> AFSEL10_R

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel9(&self) -> AFSEL9_R

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afsel8(&self) -> AFSEL8_R

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl R<u32, Reg<u32, _CR1>>

pub fn mcken(&self) -> MCKEN_R

Bit 27 - Master clock generation enable

pub fn osr(&self) -> OSR_R

Bit 26 - Oversampling ratio for master clock

pub fn mckdiv(&self) -> MCKDIV_R

Bits 20:25 - Master clock divider

pub fn nodiv(&self) -> NODIV_R

Bit 19 - No divider

pub fn dmaen(&self) -> DMAEN_R

Bit 17 - DMA enable

pub fn saien(&self) -> SAIEN_R

Bit 16 - Audio block B enable

pub fn outdriv(&self) -> OUTDRIV_R

Bit 13 - Output drive

pub fn mono(&self) -> MONO_R

Bit 12 - Mono mode

pub fn syncen(&self) -> SYNCEN_R

Bits 10:11 - Synchronization enable

pub fn ckstr(&self) -> CKSTR_R

Bit 9 - Clock strobing edge

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 8 - Least significant bit first

pub fn ds(&self) -> DS_R

Bits 5:7 - Data size

pub fn prtcfg(&self) -> PRTCFG_R

Bits 2:3 - Protocol configuration

pub fn mode(&self) -> MODE_R

Bits 0:1 - Audio block mode

impl R<u32, Reg<u32, _CR2>>

pub fn comp(&self) -> COMP_R

Bits 14:15 - Companding mode

pub fn cpl(&self) -> CPL_R

Bit 13 - Complement bit

pub fn mutecn(&self) -> MUTECN_R

Bits 7:12 - Mute counter

pub fn muteval(&self) -> MUTEVAL_R

Bit 6 - Mute value

pub fn mute(&self) -> MUTE_R

Bit 5 - Mute

pub fn tris(&self) -> TRIS_R

Bit 4 - Tristate management on data line

pub fn fflush(&self) -> FFLUSH_R

Bit 3 - FIFO flush

pub fn fth(&self) -> FTH_R

Bits 0:2 - FIFO threshold

impl R<u32, Reg<u32, _FRCR>>

pub fn fsoff(&self) -> FSOFF_R

Bit 18 - Frame synchronization offset

pub fn fspol(&self) -> FSPOL_R

Bit 17 - Frame synchronization polarity

pub fn fsdef(&self) -> FSDEF_R

Bit 16 - Frame synchronization definition

pub fn fsall(&self) -> FSALL_R

Bits 8:14 - Frame synchronization active level length

pub fn frl(&self) -> FRL_R

Bits 0:7 - Frame length

impl R<u32, Reg<u32, _SLOTR>>

pub fn sloten(&self) -> SLOTEN_R

Bits 16:31 - Slot enable

pub fn nbslot(&self) -> NBSLOT_R

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&self) -> SLOTSZ_R

Bits 6:7 - Slot size

pub fn fboff(&self) -> FBOFF_R

Bits 0:4 - First bit offset

impl R<u32, Reg<u32, _IM>>

pub fn lfsdetie(&self) -> LFSDETIE_R

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&self) -> AFSDETIE_R

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&self) -> CNRDYIE_R

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&self) -> FREQIE_R

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&self) -> WCKCFGIE_R

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&self) -> MUTEDETIE_R

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&self) -> OVRUDRIE_R

Bit 0 - Overrun/underrun interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn flvl(&self) -> FLVL_R

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&self) -> LFSDET_R

Bit 6 - Late frame synchronization detection

pub fn afsdet(&self) -> AFSDET_R

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&self) -> CNRDY_R

Bit 4 - Codec not ready

pub fn freq(&self) -> FREQ_R

Bit 3 - FIFO request

pub fn wckcfg(&self) -> WCKCFG_R

Bit 2 - Wrong clock configuration flag. This bit is read only

pub fn mutedet(&self) -> MUTEDET_R

Bit 1 - Mute detection

pub fn ovrudr(&self) -> OVRUDR_R

Bit 0 - Overrun / underrun

impl R<u32, Reg<u32, _DR>>

pub fn data(&self) -> DATA_R

Bits 0:31 - Data

impl R<u32, Reg<u32, _GCR>>

pub fn syncout(&self) -> SYNCOUT_R

Bits 4:5 - Synchronization outputs

pub fn syncin(&self) -> SYNCIN_R

Bits 0:1 - Synchronization inputs

impl R<u32, Reg<u32, _PDMCR>>

pub fn cken4(&self) -> CKEN4_R

Bit 11 - Clock enable of bitstream clock number 4

pub fn cken3(&self) -> CKEN3_R

Bit 10 - Clock enable of bitstream clock number 3

pub fn cken2(&self) -> CKEN2_R

Bit 9 - Clock enable of bitstream clock number 2

pub fn cken1(&self) -> CKEN1_R

Bit 8 - Clock enable of bitstream clock number 1

pub fn micnbr(&self) -> MICNBR_R

Bits 4:5 - Number of microphones

pub fn pdmen(&self) -> PDMEN_R

Bit 0 - PDM enable

impl R<u32, Reg<u32, _PDMDLY>>

pub fn dlym4r(&self) -> DLYM4R_R

Bits 28:30 - Delay line for second microphone of pair 4

pub fn dlym4l(&self) -> DLYM4L_R

Bits 24:26 - Delay line for first microphone of pair 4

pub fn dlym3r(&self) -> DLYM3R_R

Bits 20:22 - Delay line for second microphone of pair 3

pub fn dlym3l(&self) -> DLYM3L_R

Bits 16:18 - Delay line for first microphone of pair 3

pub fn dlym2r(&self) -> DLYM2R_R

Bits 12:14 - Delay line for second microphone of pair 2

pub fn dlym2l(&self) -> DLYM2L_R

Bits 8:10 - Delay line for first microphone of pair 2

pub fn dlym1r(&self) -> DLYM1R_R

Bits 4:6 - Delay line for second microphone of pair 1

pub fn dlym1l(&self) -> DLYM1L_R

Bits 0:2 - Delay line for first microphone of pair 1

impl R<u32, Reg<u32, _CR1>>

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

impl R<u32, Reg<u32, _CR2>>

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

impl R<u32, Reg<u32, _SMCR>>

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

impl R<u32, Reg<u32, _DIER>>

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

impl R<u32, Reg<u32, _SR>>

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&self) -> IC3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt_h(&self) -> CNT_H_R

Bits 16:30 - High counter value (TIM2 only)

pub fn cnt_l(&self) -> CNT_L_R

Bits 0:15 - Low counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - Value depends on IUFREMAP in TIM2_CR1.

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr_h(&self) -> ARR_H_R

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr_l(&self) -> ARR_L_R

Bits 0:15 - Low Auto-reload value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1_h(&self) -> CCR1_H_R

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr1_l(&self) -> CCR1_L_R

Bits 0:15 - Low Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2_h(&self) -> CCR2_H_R

Bits 16:31 - High Capture/Compare 2 value (TIM2 only)

pub fn ccr2_l(&self) -> CCR2_L_R

Bits 0:15 - Low Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3_h(&self) -> CCR3_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr3_l(&self) -> CCR3_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4_h(&self) -> CCR4_H_R

Bits 16:31 - High Capture/Compare value (TIM2 only)

pub fn ccr4_l(&self) -> CCR4_L_R

Bits 0:15 - Low Capture/Compare value

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR>>

pub fn ti4_rmp(&self) -> TI4_RMP_R

Bits 2:3 - Input capture 4 remap

pub fn etr_rmp(&self) -> ETR_RMP_R

Bit 1 - External trigger remap

pub fn itr_rmp(&self) -> ITR_RMP_R

Bit 0 - Internal trigger remap

impl R<u32, Reg<u32, _AF>>

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - External trigger source selection

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable.

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable.

pub fn urs(&self) -> URS_R

Bit 2 - Update request source.

pub fn opm(&self) -> OPM_R

Bit 3 - One pulse mode.

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable.

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division.

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping.

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable.

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable.

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable.

pub fn bie(&self) -> BIE_R

Bit 8 - Break interrupt enable.

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable.

pub fn cc1de(&self) -> CC1DE_R

Bits 9:10 - Capture/Compare 1 DMA request enable.

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR>>

pub fn ti1_rmp(&self) -> TI1_RMP_R

Bits 0:1 - Input capture 1 remap

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable.

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable.

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable.

pub fn bie(&self) -> BIE_R

Bit 8 - Break interrupt enable.

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable.

pub fn cc1de(&self) -> CC1DE_R

Bits 9:10 - Capture/Compare 1 DMA request enable.

impl R<u32, Reg<u32, _SR>>

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&self) -> OC1M_2_R

Bit 16 - Output Compare 1 mode

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&self) -> IC1F_R

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

impl R<u32, Reg<u32, _CCER>>

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF Copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:7 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR>>

pub fn ti1_rmp(&self) -> TI1_RMP_R

Bits 0:1 - Input capture 1 remap

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarit

impl R<u32, Reg<u32, _CR1>>

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable

pub fn urs(&self) -> URS_R

Bit 2 - Update request source

pub fn dir(&self) -> DIR_R

Bit 4 - Direction

pub fn cms(&self) -> CMS_R

Bits 5:6 - Center-aligned mode selection

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

impl R<u32, Reg<u32, _CR2>>

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output)

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control

impl R<u32, Reg<u32, _SMCR>>

pub fn sms(&self) -> SMS_R

Bits 0:2 - Slave mode selection

pub fn occs(&self) -> OCCS_R

Bit 3 - OCREF clear selection

pub fn ts(&self) -> TS_R

Bits 4:6 - Trigger selection

pub fn msm(&self) -> MSM_R

Bit 7 - Master/Slave mode

pub fn etf(&self) -> ETF_R

Bits 8:11 - External trigger filter

pub fn etps(&self) -> ETPS_R

Bits 12:13 - External trigger prescaler

pub fn ece(&self) -> ECE_R

Bit 14 - External clock enable

pub fn etp(&self) -> ETP_R

Bit 15 - External trigger polarity

pub fn sms_3(&self) -> SMS_3_R

Bit 16 - Slave mode selection - bit 3

impl R<u32, Reg<u32, _DIER>>

pub fn uie(&self) -> UIE_R

Bit 0 - Update interrupt enable

pub fn cc1ie(&self) -> CC1IE_R

Bit 1 - Capture/Compare 1 interrupt enable

pub fn cc2ie(&self) -> CC2IE_R

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc3ie(&self) -> CC3IE_R

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc4ie(&self) -> CC4IE_R

Bit 4 - Capture/Compare 4 interrupt enable

pub fn comie(&self) -> COMIE_R

Bit 5 - COM interrupt enable

pub fn tie(&self) -> TIE_R

Bit 6 - Trigger interrupt enable

pub fn bie(&self) -> BIE_R

Bit 7 - Break interrupt enable

pub fn ude(&self) -> UDE_R

Bit 8 - Update DMA request enable

pub fn cc1de(&self) -> CC1DE_R

Bit 9 - Capture/Compare 1 DMA request enable

pub fn cc2de(&self) -> CC2DE_R

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc3de(&self) -> CC3DE_R

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc4de(&self) -> CC4DE_R

Bit 12 - Capture/Compare 4 DMA request enable

pub fn comde(&self) -> COMDE_R

Bit 13 - COM DMA request enable

pub fn tde(&self) -> TDE_R

Bit 14 - Trigger DMA request enable

impl R<u32, Reg<u32, _SR>>

pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag

pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/compare 1 interrupt flag

pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag

pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag

pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag

pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag

pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag

pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag

pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag

pub fn cc5if(&self) -> CC5IF_R

Bit 16 - Compare 5 interrupt flag

pub fn cc6if(&self) -> CC6IF_R

Bit 17 - Compare 6 interrupt flag

impl R<u32, Reg<u32, _CCMR1_INPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn ic1psc(&self) -> IC1PSC_R

Bits 2:3 - Input capture 1 prescaler

pub fn c1f(&self) -> C1F_R

Bits 4:7 - Input capture 1 filter

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - capture/Compare 2 selection

pub fn ic2psc(&self) -> IC2PSC_R

Bits 10:11 - Input capture 2 prescaler

pub fn ic2f(&self) -> IC2F_R

Bits 12:15 - Input capture 2 filter

impl R<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable

pub fn oc1m(&self) -> OC1M_R

Bits 4:6 - Output Compare 1 mode

pub fn oc1ce(&self) -> OC1CE_R

Bit 7 - Output Compare 1 clear enable

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc2ce(&self) -> OC2CE_R

Bit 15 - Output Compare 2 clear enable

pub fn oc1m_3(&self) -> OC1M_3_R

Bit 16 - Output Compare 1 mode - bit 3

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn oc3fe(&self) -> OC3FE_R

Bit 2 - Output compare 3 fast enable

pub fn oc3pe(&self) -> OC3PE_R

Bit 3 - Output compare 3 preload enable

pub fn oc3m(&self) -> OC3M_R

Bits 4:6 - Output compare 3 mode

pub fn oc3ce(&self) -> OC3CE_R

Bit 7 - Output compare 3 clear enable

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn oc4fe(&self) -> OC4FE_R

Bit 10 - Output compare 4 fast enable

pub fn oc4pe(&self) -> OC4PE_R

Bit 11 - Output compare 4 preload enable

pub fn oc4m(&self) -> OC4M_R

Bits 12:14 - Output compare 4 mode

pub fn oc4ce(&self) -> OC4CE_R

Bit 15 - Output compare 4 clear enable

pub fn oc3m_3(&self) -> OC3M_3_R

Bit 16 - Output Compare 3 mode - bit 3

pub fn oc4m_3(&self) -> OC4M_3_R

Bit 24 - Output Compare 4 mode - bit 3

impl R<u32, Reg<u32, _CCMR2_INPUT>>

pub fn cc3s(&self) -> CC3S_R

Bits 0:1 - Capture/Compare 3 selection

pub fn c3psc(&self) -> C3PSC_R

Bits 2:3 - Input capture 3 prescaler

pub fn ic3f(&self) -> IC3F_R

Bits 4:7 - Input capture 3 filter

pub fn cc4s(&self) -> CC4S_R

Bits 8:9 - Capture/Compare 4 selection

pub fn ic4psc(&self) -> IC4PSC_R

Bits 10:11 - Input capture 4 prescaler

pub fn ic4f(&self) -> IC4F_R

Bits 12:15 - Input capture 4 filter

impl R<u32, Reg<u32, _CCER>>

pub fn cc1e(&self) -> CC1E_R

Bit 0 - Capture/Compare 1 output enable

pub fn cc1p(&self) -> CC1P_R

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1ne(&self) -> CC1NE_R

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1np(&self) -> CC1NP_R

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc2e(&self) -> CC2E_R

Bit 4 - Capture/Compare 2 output enable

pub fn cc2p(&self) -> CC2P_R

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2ne(&self) -> CC2NE_R

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2np(&self) -> CC2NP_R

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc3e(&self) -> CC3E_R

Bit 8 - Capture/Compare 3 output enable

pub fn cc3p(&self) -> CC3P_R

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3ne(&self) -> CC3NE_R

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3np(&self) -> CC3NP_R

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc4e(&self) -> CC4E_R

Bit 12 - Capture/Compare 4 output enable

pub fn cc4p(&self) -> CC4P_R

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4np(&self) -> CC4NP_R

Bit 15 - Capture/Compare 4 complementary output polarity

pub fn cc5e(&self) -> CC5E_R

Bit 16 - Capture/Compare 5 output enable

pub fn cc5p(&self) -> CC5P_R

Bit 17 - Capture/Compare 5 output polarity

pub fn cc6e(&self) -> CC6E_R

Bit 20 - Capture/Compare 6 output enable

pub fn cc6p(&self) -> CC6P_R

Bit 21 - Capture/Compare 6 output polarity

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - counter value

pub fn uifcpy(&self) -> UIFCPY_R

Bit 31 - UIF copy

impl R<u32, Reg<u32, _PSC>>

pub fn psc(&self) -> PSC_R

Bits 0:15 - Prescaler value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto-reload value

impl R<u32, Reg<u32, _RCR>>

pub fn rep(&self) -> REP_R

Bits 0:15 - Repetition counter value

impl R<u32, Reg<u32, _CCR1>>

pub fn ccr1(&self) -> CCR1_R

Bits 0:15 - Capture/Compare 1 value

impl R<u32, Reg<u32, _CCR2>>

pub fn ccr2(&self) -> CCR2_R

Bits 0:15 - Capture/Compare 2 value

impl R<u32, Reg<u32, _CCR3>>

pub fn ccr3(&self) -> CCR3_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _CCR4>>

pub fn ccr4(&self) -> CCR4_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _BDTR>>

pub fn dtg(&self) -> DTG_R

Bits 0:7 - Dead-time generator setup

pub fn lock(&self) -> LOCK_R

Bits 8:9 - Lock configuration

pub fn ossi(&self) -> OSSI_R

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&self) -> OSSR_R

Bit 11 - Off-state selection for Run mode

pub fn bke(&self) -> BKE_R

Bit 12 - Break enable

pub fn bkp(&self) -> BKP_R

Bit 13 - Break polarity

pub fn aoe(&self) -> AOE_R

Bit 14 - Automatic output enable

pub fn moe(&self) -> MOE_R

Bit 15 - Main output enable

pub fn bkf(&self) -> BKF_R

Bits 16:19 - Break filter

pub fn bk2f(&self) -> BK2F_R

Bits 20:23 - Break 2 filter

pub fn bk2e(&self) -> BK2E_R

Bit 24 - Break 2 enable

pub fn bk2p(&self) -> BK2P_R

Bit 25 - Break 2 polarity

impl R<u32, Reg<u32, _DCR>>

pub fn dbl(&self) -> DBL_R

Bits 8:12 - DMA burst length

pub fn dba(&self) -> DBA_R

Bits 0:4 - DMA base address

impl R<u32, Reg<u32, _DMAR>>

pub fn dmab(&self) -> DMAB_R

Bits 0:15 - DMA register for burst accesses

impl R<u32, Reg<u32, _OR>>

pub fn tim1_etr_adc1_rmp(&self) -> TIM1_ETR_ADC1_RMP_R

Bits 0:1 - TIM1_ETR_ADC1 remapping capability

pub fn ti1_rmp(&self) -> TI1_RMP_R

Bit 4 - Input Capture 1 remap

impl R<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&self) -> OC6M_BIT3_R

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&self) -> OC5M_BIT3_R

Bit 16 - Output Compare 5 mode bit 3

pub fn oc6ce(&self) -> OC6CE_R

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&self) -> OC6M_R

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&self) -> OC6PE_R

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&self) -> OC6FE_R

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&self) -> OC5CE_R

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&self) -> OC5M_R

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&self) -> OC5PE_R

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&self) -> OC5FE_R

Bit 2 - Output compare 5 fast enable

impl R<u32, Reg<u32, _CCR5>>

pub fn ccr5(&self) -> CCR5_R

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&self) -> GC5C1_R

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&self) -> GC5C2_R

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&self) -> GC5C3_R

Bit 31 - Group Channel 5 and Channel 3

impl R<u32, Reg<u32, _CCR6>>

pub fn ccr6(&self) -> CCR6_R

Bits 0:15 - Capture/Compare value

impl R<u32, Reg<u32, _AF1>>

pub fn bkine(&self) -> BKINE_R

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&self) -> BKCMP1E_R

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&self) -> BKCMP2E_R

Bit 2 - BRK COMP2 enable

pub fn bkinp(&self) -> BKINP_R

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&self) -> BKCMP1P_R

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&self) -> BKCMP2P_R

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&self) -> ETRSEL_R

Bits 14:16 - ETR source selection

impl R<u32, Reg<u32, _AF2>>

pub fn bk2ine(&self) -> BK2INE_R

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&self) -> BK2CMP1E_R

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&self) -> BK2CMP2E_R

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&self) -> BK2DFBK0E_R

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&self) -> BK2INP_R

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&self) -> BK2CMP1P_R

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&self) -> BK2CMP2P_R

Bit 11 - BRK2 COMP2 input polarity

impl R<u32, Reg<u32, _ISR>>

pub fn down(&self) -> DOWN_R

Bit 6 - Counter direction change up to down

pub fn up(&self) -> UP_R

Bit 5 - Counter direction change down to up

pub fn arrok(&self) -> ARROK_R

Bit 4 - Autoreload register update OK

pub fn cmpok(&self) -> CMPOK_R

Bit 3 - Compare register update OK

pub fn exttrig(&self) -> EXTTRIG_R

Bit 2 - External trigger edge event

pub fn arrm(&self) -> ARRM_R

Bit 1 - Autoreload match

pub fn cmpm(&self) -> CMPM_R

Bit 0 - Compare match

impl R<u32, Reg<u32, _IER>>

pub fn downie(&self) -> DOWNIE_R

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&self) -> UPIE_R

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&self) -> ARROKIE_R

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&self) -> CMPOKIE_R

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&self) -> EXTTRIGIE_R

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&self) -> ARRMIE_R

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&self) -> CMPMIE_R

Bit 0 - Compare match Interrupt Enable

impl R<u32, Reg<u32, _CFGR>>

pub fn enc(&self) -> ENC_R

Bit 24 - Encoder mode enable

pub fn countmode(&self) -> COUNTMODE_R

Bit 23 - counter mode enabled

pub fn preload(&self) -> PRELOAD_R

Bit 22 - Registers update mode

pub fn wavpol(&self) -> WAVPOL_R

Bit 21 - Waveform shape polarity

pub fn wave(&self) -> WAVE_R

Bit 20 - Waveform shape

pub fn timout(&self) -> TIMOUT_R

Bit 19 - Timeout enable

pub fn trigen(&self) -> TRIGEN_R

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&self) -> TRIGSEL_R

Bits 13:15 - Trigger selector

pub fn presc(&self) -> PRESC_R

Bits 9:11 - Clock prescaler

pub fn trgflt(&self) -> TRGFLT_R

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&self) -> CKFLT_R

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&self) -> CKPOL_R

Bits 1:2 - Clock Polarity

pub fn cksel(&self) -> CKSEL_R

Bit 0 - Clock selector

impl R<u32, Reg<u32, _CR>>

pub fn rstare(&self) -> RSTARE_R

Bit 4 - Reset after read enable

pub fn countrst(&self) -> COUNTRST_R

Bit 3 - Counter reset

pub fn cntstrt(&self) -> CNTSTRT_R

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&self) -> SNGSTRT_R

Bit 1 - LPTIM start in single mode

pub fn enable(&self) -> ENABLE_R

Bit 0 - LPTIM Enable

impl R<u32, Reg<u32, _CMP>>

pub fn cmp(&self) -> CMP_R

Bits 0:15 - Compare value

impl R<u32, Reg<u32, _ARR>>

pub fn arr(&self) -> ARR_R

Bits 0:15 - Auto reload value

impl R<u32, Reg<u32, _CNT>>

pub fn cnt(&self) -> CNT_R

Bits 0:15 - Counter value

impl R<u32, Reg<u32, _OR>>

pub fn or1(&self) -> OR1_R

Bit 0 - Option register bit 1

pub fn or2(&self) -> OR2_R

Bit 1 - Option register bit 2

impl R<u32, Reg<u32, _CR1>>

pub fn rxffie(&self) -> RXFFIE_R

Bit 31 - RXFIFO Full interrupt enable

pub fn txfeie(&self) -> TXFEIE_R

Bit 30 - TXFIFO empty interrupt enable

pub fn fifoen(&self) -> FIFOEN_R

Bit 29 - FIFO mode enable

pub fn m1(&self) -> M1_R

Bit 28 - Word length

pub fn eobie(&self) -> EOBIE_R

Bit 27 - End of Block interrupt enable

pub fn rtoie(&self) -> RTOIE_R

Bit 26 - Receiver timeout interrupt enable

pub fn deat4(&self) -> DEAT4_R

Bit 25 - Driver Enable assertion time

pub fn deat3(&self) -> DEAT3_R

Bit 24 - DEAT3

pub fn deat2(&self) -> DEAT2_R

Bit 23 - DEAT2

pub fn deat1(&self) -> DEAT1_R

Bit 22 - DEAT1

pub fn deat0(&self) -> DEAT0_R

Bit 21 - DEAT0

pub fn dedt4(&self) -> DEDT4_R

Bit 20 - Driver Enable de-assertion time

pub fn dedt3(&self) -> DEDT3_R

Bit 19 - DEDT3

pub fn dedt2(&self) -> DEDT2_R

Bit 18 - DEDT2

pub fn dedt1(&self) -> DEDT1_R

Bit 17 - DEDT1

pub fn dedt0(&self) -> DEDT0_R

Bit 16 - DEDT0

pub fn over8(&self) -> OVER8_R

Bit 15 - Oversampling mode

pub fn cmie(&self) -> CMIE_R

Bit 14 - Character match interrupt enable

pub fn mme(&self) -> MME_R

Bit 13 - Mute mode enable

pub fn m0(&self) -> M0_R

Bit 12 - Word length

pub fn wake(&self) -> WAKE_R

Bit 11 - Receiver wakeup method

pub fn pce(&self) -> PCE_R

Bit 10 - Parity control enable

pub fn ps(&self) -> PS_R

Bit 9 - Parity selection

pub fn peie(&self) -> PEIE_R

Bit 8 - PE interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - interrupt enable

pub fn tcie(&self) -> TCIE_R

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 5 - RXNE interrupt enable

pub fn idleie(&self) -> IDLEIE_R

Bit 4 - IDLE interrupt enable

pub fn te(&self) -> TE_R

Bit 3 - Transmitter enable

pub fn re(&self) -> RE_R

Bit 2 - Receiver enable

pub fn uesm(&self) -> UESM_R

Bit 1 - USART enable in Stop mode

pub fn ue(&self) -> UE_R

Bit 0 - USART enable

impl R<u32, Reg<u32, _CR2>>

pub fn add4_7(&self) -> ADD4_7_R

Bits 28:31 - Address of the USART node

pub fn add0_3(&self) -> ADD0_3_R

Bits 24:27 - Address of the USART node

pub fn rtoen(&self) -> RTOEN_R

Bit 23 - Receiver timeout enable

pub fn abrmod1(&self) -> ABRMOD1_R

Bit 22 - Auto baud rate mode

pub fn abrmod0(&self) -> ABRMOD0_R

Bit 21 - ABRMOD0

pub fn abren(&self) -> ABREN_R

Bit 20 - Auto baud rate enable

pub fn msbfirst(&self) -> MSBFIRST_R

Bit 19 - Most significant bit first

pub fn tainv(&self) -> TAINV_R

Bit 18 - Binary data inversion

pub fn txinv(&self) -> TXINV_R

Bit 17 - TX pin active level inversion

pub fn rxinv(&self) -> RXINV_R

Bit 16 - RX pin active level inversion

pub fn swap(&self) -> SWAP_R

Bit 15 - Swap TX/RX pins

pub fn linen(&self) -> LINEN_R

Bit 14 - LIN mode enable

pub fn stop(&self) -> STOP_R

Bits 12:13 - STOP bits

pub fn clken(&self) -> CLKEN_R

Bit 11 - Clock enable

pub fn cpol(&self) -> CPOL_R

Bit 10 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 9 - Clock phase

pub fn lbcl(&self) -> LBCL_R

Bit 8 - Last bit clock pulse

pub fn lbdie(&self) -> LBDIE_R

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&self) -> LBDL_R

Bit 5 - LIN break detection length

pub fn addm7(&self) -> ADDM7_R

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn dis_nss(&self) -> DIS_NSS_R

Bit 3 - When the DSI_NSS bit is set, the NSS pin input will be ignored

pub fn slven(&self) -> SLVEN_R

Bit 0 - Synchronous Slave mode enable

impl R<u32, Reg<u32, _CR3>>

pub fn txftcfg(&self) -> TXFTCFG_R

Bits 29:31 - TXFIFO threshold configuration

pub fn rxftie(&self) -> RXFTIE_R

Bit 28 - RXFIFO threshold interrupt enable

pub fn rxftcfg(&self) -> RXFTCFG_R

Bits 25:27 - Receive FIFO threshold configuration

pub fn tcbgtie(&self) -> TCBGTIE_R

Bit 24 - Tr Complete before guard time, interrupt enable

pub fn txftie(&self) -> TXFTIE_R

Bit 23 - threshold interrupt enable

pub fn wufie(&self) -> WUFIE_R

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&self) -> WUS_R

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&self) -> SCARCNT_R

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&self) -> DEP_R

Bit 15 - Driver enable polarity selection

pub fn dem(&self) -> DEM_R

Bit 14 - Driver enable mode

pub fn ddre(&self) -> DDRE_R

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&self) -> OVRDIS_R

Bit 12 - Overrun Disable

pub fn onebit(&self) -> ONEBIT_R

Bit 11 - One sample bit method enable

pub fn ctsie(&self) -> CTSIE_R

Bit 10 - CTS interrupt enable

pub fn ctse(&self) -> CTSE_R

Bit 9 - CTS enable

pub fn rtse(&self) -> RTSE_R

Bit 8 - RTS enable

pub fn dmat(&self) -> DMAT_R

Bit 7 - DMA enable transmitter

pub fn dmar(&self) -> DMAR_R

Bit 6 - DMA enable receiver

pub fn scen(&self) -> SCEN_R

Bit 5 - Smartcard mode enable

pub fn nack(&self) -> NACK_R

Bit 4 - Smartcard NACK enable

pub fn hdsel(&self) -> HDSEL_R

Bit 3 - Half-duplex selection

pub fn irlp(&self) -> IRLP_R

Bit 2 - Ir low-power

pub fn iren(&self) -> IREN_R

Bit 1 - Ir mode enable

pub fn eie(&self) -> EIE_R

Bit 0 - Error interrupt enable

impl R<u32, Reg<u32, _BRR>>

pub fn brr(&self) -> BRR_R

Bits 0:15 - BRR_4_15

impl R<u32, Reg<u32, _GTPR>>

pub fn gt(&self) -> GT_R

Bits 8:15 - Guard time value

pub fn psc(&self) -> PSC_R

Bits 0:7 - Prescaler value

impl R<u32, Reg<u32, _RTOR>>

pub fn blen(&self) -> BLEN_R

Bits 24:31 - Block Length

pub fn rto(&self) -> RTO_R

Bits 0:23 - Receiver timeout value

impl R<u32, Reg<u32, _ISR>>

pub fn txft(&self) -> TXFT_R

Bit 27 - TXFIFO threshold flag

pub fn rxft(&self) -> RXFT_R

Bit 26 - RXFIFO threshold flag

pub fn tcbgt(&self) -> TCBGT_R

Bit 25 - Transmission complete before guard time flag

pub fn rxff(&self) -> RXFF_R

Bit 24 - RXFIFO Full

pub fn txfe(&self) -> TXFE_R

Bit 23 - TXFIFO Empty

pub fn reack(&self) -> REACK_R

Bit 22 - REACK

pub fn teack(&self) -> TEACK_R

Bit 21 - TEACK

pub fn wuf(&self) -> WUF_R

Bit 20 - WUF

pub fn rwu(&self) -> RWU_R

Bit 19 - RWU

pub fn sbkf(&self) -> SBKF_R

Bit 18 - SBKF

pub fn cmf(&self) -> CMF_R

Bit 17 - CMF

pub fn busy(&self) -> BUSY_R

Bit 16 - BUSY

pub fn abrf(&self) -> ABRF_R

Bit 15 - ABRF

pub fn abre(&self) -> ABRE_R

Bit 14 - ABRE

pub fn udr(&self) -> UDR_R

Bit 13 - SPI slave underrun error flag

pub fn eobf(&self) -> EOBF_R

Bit 12 - EOBF

pub fn rtof(&self) -> RTOF_R

Bit 11 - RTOF

pub fn cts(&self) -> CTS_R

Bit 10 - CTS

pub fn ctsif(&self) -> CTSIF_R

Bit 9 - CTSIF

pub fn lbdf(&self) -> LBDF_R

Bit 8 - LBDF

pub fn txe(&self) -> TXE_R

Bit 7 - TXE

pub fn tc(&self) -> TC_R

Bit 6 - TC

pub fn rxne(&self) -> RXNE_R

Bit 5 - RXNE

pub fn idle(&self) -> IDLE_R

Bit 4 - IDLE

pub fn ore(&self) -> ORE_R

Bit 3 - ORE

pub fn nf(&self) -> NF_R

Bit 2 - NF

pub fn fe(&self) -> FE_R

Bit 1 - FE

pub fn pe(&self) -> PE_R

Bit 0 - PE

impl R<u32, Reg<u32, _RDR>>

pub fn rdr(&self) -> RDR_R

Bits 0:8 - Receive data value

impl R<u32, Reg<u32, _TDR>>

pub fn tdr(&self) -> TDR_R

Bits 0:8 - Transmit data value

impl R<u32, Reg<u32, _PRESC>>

pub fn prescaler(&self) -> PRESCALER_R

Bits 0:3 - Clock prescaler

impl R<u32, Reg<u32, _CR1>>

pub fn bidimode(&self) -> BIDIMODE_R

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&self) -> BIDIOE_R

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&self) -> CRCEN_R

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&self) -> CRCNEXT_R

Bit 12 - CRC transfer next

pub fn dff(&self) -> DFF_R

Bit 11 - Data frame format

pub fn rxonly(&self) -> RXONLY_R

Bit 10 - Receive only

pub fn ssm(&self) -> SSM_R

Bit 9 - Software slave management

pub fn ssi(&self) -> SSI_R

Bit 8 - Internal slave select

pub fn lsbfirst(&self) -> LSBFIRST_R

Bit 7 - Frame format

pub fn spe(&self) -> SPE_R

Bit 6 - SPI enable

pub fn br(&self) -> BR_R

Bits 3:5 - Baud rate control

pub fn mstr(&self) -> MSTR_R

Bit 2 - Master selection

pub fn cpol(&self) -> CPOL_R

Bit 1 - Clock polarity

pub fn cpha(&self) -> CPHA_R

Bit 0 - Clock phase

impl R<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&self) -> RXDMAEN_R

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&self) -> TXDMAEN_R

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&self) -> SSOE_R

Bit 2 - SS output enable

pub fn nssp(&self) -> NSSP_R

Bit 3 - NSS pulse management

pub fn frf(&self) -> FRF_R

Bit 4 - Frame format

pub fn errie(&self) -> ERRIE_R

Bit 5 - Error interrupt enable

pub fn rxneie(&self) -> RXNEIE_R

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&self) -> TXEIE_R

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&self) -> DS_R

Bits 8:11 - Data size

pub fn frxth(&self) -> FRXTH_R

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&self) -> LDMA_RX_R

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&self) -> LDMA_TX_R

Bit 14 - Last DMA transfer for transmission

impl R<u32, Reg<u32, _SR>>

pub fn rxne(&self) -> RXNE_R

Bit 0 - Receive buffer not empty

pub fn txe(&self) -> TXE_R

Bit 1 - Transmit buffer empty

pub fn crcerr(&self) -> CRCERR_R

Bit 4 - CRC error flag

pub fn modf(&self) -> MODF_R

Bit 5 - Mode fault

pub fn ovr(&self) -> OVR_R

Bit 6 - Overrun flag

pub fn bsy(&self) -> BSY_R

Bit 7 - Busy flag

pub fn tifrfe(&self) -> TIFRFE_R

Bit 8 - TI frame format error

pub fn frlvl(&self) -> FRLVL_R

Bits 9:10 - FIFO reception level

pub fn ftlvl(&self) -> FTLVL_R

Bits 11:12 - FIFO transmission level

impl R<u32, Reg<u32, _DR>>

pub fn dr(&self) -> DR_R

Bits 0:15 - Data register

impl R<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&self) -> CRCPOLY_R

Bits 0:15 - CRC polynomial register

impl R<u32, Reg<u32, _RXCRCR>>

pub fn rx_crc(&self) -> RXCRC_R

Bits 0:15 - Rx CRC register

impl R<u32, Reg<u32, _TXCRCR>>

pub fn tx_crc(&self) -> TXCRC_R

Bits 0:15 - Tx CRC register

impl R<u32, Reg<u32, _CSR>>

pub fn envr(&self) -> ENVR_R

Bit 0 - Voltage reference buffer enable

pub fn hiz(&self) -> HIZ_R

Bit 1 - High impedance mode

pub fn vrs(&self) -> VRS_R

Bit 2 - Voltage reference scale

pub fn vrr(&self) -> VRR_R

Bit 3 - Voltage reference buffer ready

impl R<u32, Reg<u32, _CCR>>

pub fn trim(&self) -> TRIM_R

Bits 0:5 - Trimming code

impl R<u32, Reg<u32, _TR>>

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _DR>>

pub fn yt(&self) -> YT_R

Bits 20:23 - Year tens in BCD format

pub fn yu(&self) -> YU_R

Bits 16:19 - Year units in BCD format

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _CR>>

pub fn wucksel(&self) -> WUCKSEL_R

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&self) -> TSEDGE_R

Bit 3 - Time-stamp event active edge

pub fn refckon(&self) -> REFCKON_R

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&self) -> BYPSHAD_R

Bit 5 - Bypass the shadow registers

pub fn fmt(&self) -> FMT_R

Bit 6 - Hour format

pub fn alrae(&self) -> ALRAE_R

Bit 8 - Alarm A enable

pub fn alrbe(&self) -> ALRBE_R

Bit 9 - Alarm B enable

pub fn wute(&self) -> WUTE_R

Bit 10 - Wakeup timer enable

pub fn tse(&self) -> TSE_R

Bit 11 - Time stamp enable

pub fn alraie(&self) -> ALRAIE_R

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&self) -> ALRBIE_R

Bit 13 - Alarm B interrupt enable

pub fn wutie(&self) -> WUTIE_R

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&self) -> TSIE_R

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&self) -> ADD1H_R

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&self) -> SUB1H_R

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&self) -> BKP_R

Bit 18 - Backup

pub fn cosel(&self) -> COSEL_R

Bit 19 - Calibration output selection

pub fn pol(&self) -> POL_R

Bit 20 - Output polarity

pub fn osel(&self) -> OSEL_R

Bits 21:22 - Output selection

pub fn coe(&self) -> COE_R

Bit 23 - Calibration output enable

pub fn itse(&self) -> ITSE_R

Bit 24 - timestamp on internal event enable

impl R<u32, Reg<u32, _ISR>>

pub fn alrawf(&self) -> ALRAWF_R

Bit 0 - Alarm A write flag

pub fn alrbwf(&self) -> ALRBWF_R

Bit 1 - Alarm B write flag

pub fn wutwf(&self) -> WUTWF_R

Bit 2 - Wakeup timer write flag

pub fn shpf(&self) -> SHPF_R

Bit 3 - Shift operation pending

pub fn inits(&self) -> INITS_R

Bit 4 - Initialization status flag

pub fn rsf(&self) -> RSF_R

Bit 5 - Registers synchronization flag

pub fn initf(&self) -> INITF_R

Bit 6 - Initialization flag

pub fn init(&self) -> INIT_R

Bit 7 - Initialization mode

pub fn alraf(&self) -> ALRAF_R

Bit 8 - Alarm A flag

pub fn alrbf(&self) -> ALRBF_R

Bit 9 - Alarm B flag

pub fn wutf(&self) -> WUTF_R

Bit 10 - Wakeup timer flag

pub fn tsf(&self) -> TSF_R

Bit 11 - Time-stamp flag

pub fn tsovf(&self) -> TSOVF_R

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&self) -> TAMP1F_R

Bit 13 - Tamper detection flag

pub fn tamp2f(&self) -> TAMP2F_R

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&self) -> TAMP3F_R

Bit 15 - RTC_TAMP3 detection flag

pub fn recalpf(&self) -> RECALPF_R

Bit 16 - Recalibration pending Flag

pub fn itsf(&self) -> ITSF_R

Bit 17 - INTERNAL TIME-STAMP FLAG

impl R<u32, Reg<u32, _PRER>>

pub fn prediv_a(&self) -> PREDIV_A_R

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&self) -> PREDIV_S_R

Bits 0:14 - Synchronous prescaler factor

impl R<u32, Reg<u32, _WUTR>>

pub fn wut(&self) -> WUT_R

Bits 0:15 - Wakeup auto-reload value bits

impl R<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm A date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm A hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm A minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm A seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&self) -> MSK4_R

Bit 31 - Alarm B date mask

pub fn wdsel(&self) -> WDSEL_R

Bit 30 - Week day selection

pub fn dt(&self) -> DT_R

Bits 28:29 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&self) -> MSK3_R

Bit 23 - Alarm B hours mask

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn msk2(&self) -> MSK2_R

Bit 15 - Alarm B minutes mask

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn msk1(&self) -> MSK1_R

Bit 7 - Alarm B seconds mask

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

impl R<u32, Reg<u32, _SSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _TSTR>>

pub fn su(&self) -> SU_R

Bits 0:3 - Second units in BCD format

pub fn st(&self) -> ST_R

Bits 4:6 - Second tens in BCD format

pub fn mnu(&self) -> MNU_R

Bits 8:11 - Minute units in BCD format

pub fn mnt(&self) -> MNT_R

Bits 12:14 - Minute tens in BCD format

pub fn hu(&self) -> HU_R

Bits 16:19 - Hour units in BCD format

pub fn ht(&self) -> HT_R

Bits 20:21 - Hour tens in BCD format

pub fn pm(&self) -> PM_R

Bit 22 - AM/PM notation

impl R<u32, Reg<u32, _TSDR>>

pub fn wdu(&self) -> WDU_R

Bits 13:15 - Week day units

pub fn mt(&self) -> MT_R

Bit 12 - Month tens in BCD format

pub fn mu(&self) -> MU_R

Bits 8:11 - Month units in BCD format

pub fn dt(&self) -> DT_R

Bits 4:5 - Date tens in BCD format

pub fn du(&self) -> DU_R

Bits 0:3 - Date units in BCD format

impl R<u32, Reg<u32, _TSSSR>>

pub fn ss(&self) -> SS_R

Bits 0:15 - Sub second value

impl R<u32, Reg<u32, _CALR>>

pub fn calp(&self) -> CALP_R

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&self) -> CALW8_R

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&self) -> CALW16_R

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&self) -> CALM_R

Bits 0:8 - Calibration minus

impl R<u32, Reg<u32, _TAMPCR>>

pub fn tamp1e(&self) -> TAMP1E_R

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&self) -> TAMP1TRG_R

Bit 1 - Active level for tamper 1

pub fn tampie(&self) -> TAMPIE_R

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&self) -> TAMP2E_R

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&self) -> TAMP2TRG_R

Bit 4 - Active level for tamper 2

pub fn tamp3e(&self) -> TAMP3E_R

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&self) -> TAMP3TRG_R

Bit 6 - Active level for tamper 3

pub fn tampts(&self) -> TAMPTS_R

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&self) -> TAMPFREQ_R

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&self) -> TAMPFLT_R

Bits 11:12 - Tamper filter count

pub fn tampprch(&self) -> TAMPPRCH_R

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&self) -> TAMPPUDIS_R

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&self) -> TAMP1IE_R

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&self) -> TAMP1NOERASE_R

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&self) -> TAMP1MF_R

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&self) -> TAMP2IE_R

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&self) -> TAMP2NOERASE_R

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&self) -> TAMP2MF_R

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&self) -> TAMP3IE_R

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&self) -> TAMP3NOERASE_R

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&self) -> TAMP3MF_R

Bit 24 - Tamper 3 mask flag

impl R<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&self) -> MASKSS_R

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&self) -> SS_R

Bits 0:14 - Sub seconds value

impl R<u32, Reg<u32, _OR>>

pub fn rtc_alarm_type(&self) -> RTC_ALARM_TYPE_R

Bit 0 - RTC_ALARM on PC13 output type

pub fn rtc_out_rmp(&self) -> RTC_OUT_RMP_R

Bit 1 - RTC_OUT remap

impl R<u32, Reg<u32, _BKP0R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP1R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP2R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP3R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP4R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP5R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP6R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP7R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP8R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP9R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP10R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP11R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP12R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP13R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP14R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP15R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP16R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP17R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP18R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _BKP19R>>

pub fn bkp(&self) -> BKP_R

Bits 0:31 - BKP

impl R<u32, Reg<u32, _IDCODE>>

pub fn dev_id(&self) -> DEV_ID_R

Bits 0:11 - Device Identifier

pub fn rev_id(&self) -> REV_ID_R

Bits 16:31 - Revision Identifier

impl R<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&self) -> DBG_SLEEP_R

Bit 0 - Debug Sleep Mode

pub fn dbg_stop(&self) -> DBG_STOP_R

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&self) -> DBG_STANDBY_R

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&self) -> TRACE_IOEN_R

Bit 5 - Trace port and clock enable

pub fn trgoen(&self) -> TRGOEN_R

Bit 28 - External trigger output enable

impl R<u32, Reg<u32, _APB1FZR1>>

pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R

Bit 11 - WWDG counter stopped when core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - IWDG counter stopped when core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted

pub fn dbg_i2c3_stop(&self) -> DBG_I2C3_STOP_R

Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - Debug LPTIM1 stopped when Core is halted

impl R<u32, Reg<u32, _C2AP_B1FZR1>>

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 0 - LPTIM2 counter stopped when core is halted

pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R

Bit 12 - IWDG stopped when core is halted

pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R

Bit 21 - I2C1 SMBUS timeout stopped when core is halted

pub fn dbg_i2c3_stop(&self) -> DBG_I2C3_STOP_R

Bit 23 - I2C3 SMBUS timeout stopped when core is halted

pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R

Bit 31 - LPTIM1 counter stopped when core is halted

impl R<u32, Reg<u32, _APB1FZR2>>

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 5 - LPTIM2 counter stopped when core is halted

impl R<u32, Reg<u32, _C2APB1FZR2>>

pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R

Bit 5 - LPTIM2 counter stopped when core is halted

impl R<u32, Reg<u32, _APB2FZR>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - TIM17 counter stopped when core is halted

impl R<u32, Reg<u32, _C2APB2FZR>>

pub fn dbg_tim1_stop(&self) -> DBG_TIM1_STOP_R

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim16_stop(&self) -> DBG_TIM16_STOP_R

Bit 17 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&self) -> DBG_TIM17_STOP_R

Bit 18 - TIM17 counter stopped when core is halted

impl R<u32, Reg<u32, _CR>>

pub fn addrerrie(&self) -> ADDRERRIE_R

Bit 20 - Address error interrupt enable

pub fn ramerrie(&self) -> RAMERRIE_R

Bit 19 - RAM error interrupt enable

pub fn procendie(&self) -> PROCENDIE_R

Bit 17 - End of operation interrupt enable

pub fn mode(&self) -> MODE_R

Bits 8:13 - PKA Operation Mode

pub fn seclvl(&self) -> SECLVL_R

Bit 2 - Security Enable

pub fn start(&self) -> START_R

Bit 1 - Start the operation

pub fn en(&self) -> EN_R

Bit 0 - Peripheral Enable

impl R<u32, Reg<u32, _SR>>

pub fn addrerrf(&self) -> ADDRERRF_R

Bit 20 - Address error flag

pub fn ramerrf(&self) -> RAMERRF_R

Bit 19 - RAM error flag

pub fn procendf(&self) -> PROCENDF_R

Bit 17 - PKA End of Operation flag

pub fn busy(&self) -> BUSY_R

Bit 16 - PKA Operation in progress

impl R<u32, Reg<u32, _CLRFR>>

pub fn addrerrfc(&self) -> ADDRERRFC_R

Bit 20 - Clear Address error flag

pub fn ramerrfc(&self) -> RAMERRFC_R

Bit 19 - Clear RAM error flag

pub fn procendfc(&self) -> PROCENDFC_R

Bit 17 - Clear PKA End of Operation flag

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor revision

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn id(&self) -> ID_R

Bits 0:31 - Identification Code

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Side Identification Code

impl R<u32, Reg<u32, _C1CR>>

pub fn txfie(&self) -> TXFIE_R

Bit 16 - processor 1 Transmit channel free interrupt enable

pub fn rxoie(&self) -> RXOIE_R

Bit 0 - processor 1 Receive channel occupied interrupt enable

impl R<u32, Reg<u32, _C1MR>>

pub fn ch6fm(&self) -> CH6FM_R

Bit 21 - processor 1 Transmit channel 6 free interrupt mask

pub fn ch5fm(&self) -> CH5FM_R

Bit 20 - processor 1 Transmit channel 5 free interrupt mask

pub fn ch4fm(&self) -> CH4FM_R

Bit 19 - processor 1 Transmit channel 4 free interrupt mask

pub fn ch3fm(&self) -> CH3FM_R

Bit 18 - processor 1 Transmit channel 3 free interrupt mask

pub fn ch2fm(&self) -> CH2FM_R

Bit 17 - processor 1 Transmit channel 2 free interrupt mask

pub fn ch1fm(&self) -> CH1FM_R

Bit 16 - processor 1 Transmit channel 1 free interrupt mask

pub fn ch6om(&self) -> CH6OM_R

Bit 5 - processor 1 Receive channel 6 occupied interrupt enable

pub fn ch5om(&self) -> CH5OM_R

Bit 4 - processor 1 Receive channel 5 occupied interrupt enable

pub fn ch4om(&self) -> CH4OM_R

Bit 3 - processor 1 Receive channel 4 occupied interrupt enable

pub fn ch3om(&self) -> CH3OM_R

Bit 2 - processor 1 Receive channel 3 occupied interrupt enable

pub fn ch2om(&self) -> CH2OM_R

Bit 1 - processor 1 Receive channel 2 occupied interrupt enable

pub fn ch1om(&self) -> CH1OM_R

Bit 0 - processor 1 Receive channel 1 occupied interrupt enable

impl R<u32, Reg<u32, _C1TOC2SR>>

pub fn ch6f(&self) -> CH6F_R

Bit 5 - processor 1 transmit to process 2 Receive channel 6 status flag

pub fn ch5f(&self) -> CH5F_R

Bit 4 - processor 1 transmit to process 2 Receive channel 5 status flag

pub fn ch4f(&self) -> CH4F_R

Bit 3 - processor 1 transmit to process 2 Receive channel 4 status flag

pub fn ch3f(&self) -> CH3F_R

Bit 2 - processor 1 transmit to process 2 Receive channel 3 status flag

pub fn ch2f(&self) -> CH2F_R

Bit 1 - processor 1 transmit to process 2 Receive channel 2 status flag

pub fn ch1f(&self) -> CH1F_R

Bit 0 - processor 1 transmit to process 2 Receive channel 1 status flag

impl R<u32, Reg<u32, _C2CR>>

pub fn txfie(&self) -> TXFIE_R

Bit 16 - processor 2 Transmit channel free interrupt enable

pub fn rxoie(&self) -> RXOIE_R

Bit 0 - processor 2 Receive channel occupied interrupt enable

impl R<u32, Reg<u32, _C2MR>>

pub fn ch6fm(&self) -> CH6FM_R

Bit 21 - processor 2 Transmit channel 6 free interrupt mask

pub fn ch5fm(&self) -> CH5FM_R

Bit 20 - processor 2 Transmit channel 5 free interrupt mask

pub fn ch4fm(&self) -> CH4FM_R

Bit 19 - processor 2 Transmit channel 4 free interrupt mask

pub fn ch3fm(&self) -> CH3FM_R

Bit 18 - processor 2 Transmit channel 3 free interrupt mask

pub fn ch2fm(&self) -> CH2FM_R

Bit 17 - processor 2 Transmit channel 2 free interrupt mask

pub fn ch1fm(&self) -> CH1FM_R

Bit 16 - processor 2 Transmit channel 1 free interrupt mask

pub fn ch6om(&self) -> CH6OM_R

Bit 5 - processor 2 Receive channel 6 occupied interrupt enable

pub fn ch5om(&self) -> CH5OM_R

Bit 4 - processor 2 Receive channel 5 occupied interrupt enable

pub fn ch4om(&self) -> CH4OM_R

Bit 3 - processor 2 Receive channel 4 occupied interrupt enable

pub fn ch3om(&self) -> CH3OM_R

Bit 2 - processor 2 Receive channel 3 occupied interrupt enable

pub fn ch2om(&self) -> CH2OM_R

Bit 1 - processor 2 Receive channel 2 occupied interrupt enable

pub fn ch1om(&self) -> CH1OM_R

Bit 0 - processor 2 Receive channel 1 occupied interrupt enable

impl R<u32, Reg<u32, _C2TOC1SR>>

pub fn ch6f(&self) -> CH6F_R

Bit 5 - processor 2 transmit to process 1 Receive channel 6 status flag

pub fn ch5f(&self) -> CH5F_R

Bit 4 - processor 2 transmit to process 1 Receive channel 5 status flag

pub fn ch4f(&self) -> CH4F_R

Bit 3 - processor 2 transmit to process 1 Receive channel 4 status flag

pub fn ch3f(&self) -> CH3F_R

Bit 2 - processor 2 transmit to process 1 Receive channel 3 status flag

pub fn ch2f(&self) -> CH2F_R

Bit 1 - processor 2 transmit to process 1 Receive channel 2 status flag

pub fn ch1f(&self) -> CH1F_R

Bit 0 - processor 2 transmit to process 1 Receive channel 1 status flag

impl R<u32, Reg<u32, _HWCFGR>>

pub fn channels(&self) -> CHANNELS_R

Bits 0:7 - Number of channels per CPU supported by the IP, range 1 to 16

impl R<u32, Reg<u32, _VERR>>

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - Identification Code

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification Code

impl R<u32, Reg<u32, _RTSR1>>

pub fn rt(&self) -> RT_R

Bits 0:21 - Rising trigger event configuration bit of Configurable Event input

pub fn rt_31(&self) -> RT_31_R

Bit 31 - Rising trigger event configuration bit of Configurable Event input

pub fn rt0(&self) -> RT0_R

Bit 0 - Rising trigger event configuration bit of configurable Event input 0.

pub fn rt1(&self) -> RT1_R

Bit 1 - Rising trigger event configuration bit of configurable Event input 1.

pub fn rt2(&self) -> RT2_R

Bit 2 - Rising trigger event configuration bit of configurable Event input 2.

pub fn rt3(&self) -> RT3_R

Bit 3 - Rising trigger event configuration bit of configurable Event input 3.

pub fn rt4(&self) -> RT4_R

Bit 4 - Rising trigger event configuration bit of configurable Event input 4.

pub fn rt5(&self) -> RT5_R

Bit 5 - Rising trigger event configuration bit of configurable Event input 5.

pub fn rt6(&self) -> RT6_R

Bit 6 - Rising trigger event configuration bit of configurable Event input 6.

pub fn rt7(&self) -> RT7_R

Bit 7 - Rising trigger event configuration bit of configurable Event input 7.

pub fn rt8(&self) -> RT8_R

Bit 8 - Rising trigger event configuration bit of configurable Event input 8.

pub fn rt9(&self) -> RT9_R

Bit 9 - Rising trigger event configuration bit of configurable Event input 9.

pub fn rt10(&self) -> RT10_R

Bit 10 - Rising trigger event configuration bit of configurable Event input 10.

pub fn rt11(&self) -> RT11_R

Bit 11 - Rising trigger event configuration bit of configurable Event input 11.

pub fn rt12(&self) -> RT12_R

Bit 12 - Rising trigger event configuration bit of configurable Event input 12.

pub fn rt13(&self) -> RT13_R

Bit 13 - Rising trigger event configuration bit of configurable Event input 13.

pub fn rt14(&self) -> RT14_R

Bit 14 - Rising trigger event configuration bit of configurable Event input 14.

pub fn rt15(&self) -> RT15_R

Bit 15 - Rising trigger event configuration bit of configurable Event input 15.

pub fn rt16(&self) -> RT16_R

Bit 16 - Rising trigger event configuration bit of configurable Event input 16.

pub fn rt17(&self) -> RT17_R

Bit 17 - Rising trigger event configuration bit of configurable Event input 17.

pub fn rt18(&self) -> RT18_R

Bit 18 - Rising trigger event configuration bit of configurable Event input 18.

pub fn rt19(&self) -> RT19_R

Bit 19 - Rising trigger event configuration bit of configurable Event input 19.

pub fn rt20(&self) -> RT20_R

Bit 20 - Rising trigger event configuration bit of configurable Event input 20.

pub fn rt21(&self) -> RT21_R

Bit 21 - Rising trigger event configuration bit of configurable Event input 21.

pub fn rt31(&self) -> RT31_R

Bit 31 - Rising trigger event configuration bit of configurable Event input 31.

impl R<u32, Reg<u32, _FTSR1>>

pub fn ft(&self) -> FT_R

Bits 0:21 - Falling trigger event configuration bit of Configurable Event input

pub fn ft_31(&self) -> FT_31_R

Bit 31 - Falling trigger event configuration bit of Configurable Event input

pub fn ft0(&self) -> FT0_R

Bit 0 - Falling trigger event configuration bit of configurable Event input 0.

pub fn ft1(&self) -> FT1_R

Bit 1 - Falling trigger event configuration bit of configurable Event input 1.

pub fn ft2(&self) -> FT2_R

Bit 2 - Falling trigger event configuration bit of configurable Event input 2.

pub fn ft3(&self) -> FT3_R

Bit 3 - Falling trigger event configuration bit of configurable Event input 3.

pub fn ft4(&self) -> FT4_R

Bit 4 - Falling trigger event configuration bit of configurable Event input 4.

pub fn ft5(&self) -> FT5_R

Bit 5 - Falling trigger event configuration bit of configurable Event input 5.

pub fn ft6(&self) -> FT6_R

Bit 6 - Falling trigger event configuration bit of configurable Event input 6.

pub fn ft7(&self) -> FT7_R

Bit 7 - Falling trigger event configuration bit of configurable Event input 7.

pub fn ft8(&self) -> FT8_R

Bit 8 - Falling trigger event configuration bit of configurable Event input 8.

pub fn ft9(&self) -> FT9_R

Bit 9 - Falling trigger event configuration bit of configurable Event input 9.

pub fn ft10(&self) -> FT10_R

Bit 10 - Falling trigger event configuration bit of configurable Event input 10.

pub fn ft11(&self) -> FT11_R

Bit 11 - Falling trigger event configuration bit of configurable Event input 11.

pub fn ft12(&self) -> FT12_R

Bit 12 - Falling trigger event configuration bit of configurable Event input 12.

pub fn ft13(&self) -> FT13_R

Bit 13 - Falling trigger event configuration bit of configurable Event input 13.

pub fn ft14(&self) -> FT14_R

Bit 14 - Falling trigger event configuration bit of configurable Event input 14.

pub fn ft15(&self) -> FT15_R

Bit 15 - Falling trigger event configuration bit of configurable Event input 15.

pub fn ft16(&self) -> FT16_R

Bit 16 - Falling trigger event configuration bit of configurable Event input 16.

pub fn ft17(&self) -> FT17_R

Bit 17 - Falling trigger event configuration bit of configurable Event input 17.

pub fn ft18(&self) -> FT18_R

Bit 18 - Falling trigger event configuration bit of configurable Event input 18.

pub fn ft19(&self) -> FT19_R

Bit 19 - Falling trigger event configuration bit of configurable Event input 19.

pub fn ft20(&self) -> FT20_R

Bit 20 - Falling trigger event configuration bit of configurable Event input 20.

pub fn ft21(&self) -> FT21_R

Bit 21 - Falling trigger event configuration bit of configurable Event input 21.

pub fn ft31(&self) -> FT31_R

Bit 31 - Falling trigger event configuration bit of configurable Event input 31.

impl R<u32, Reg<u32, _SWIER1>>

pub fn swi(&self) -> SWI_R

Bits 0:21 - Software interrupt on event

pub fn swi_31(&self) -> SWI_31_R

Bit 31 - Software interrupt on event

impl R<u32, Reg<u32, _PR1>>

pub fn pif(&self) -> PIF_R

Bits 0:21 - Configurable event inputs Pending bit

pub fn pif_31(&self) -> PIF_31_R

Bit 31 - Configurable event inputs Pending bit

impl R<u32, Reg<u32, _RTSR2>>

pub fn rt33(&self) -> RT33_R

Bit 1 - Rising trigger event configuration bit of Configurable Event input

pub fn rt40_41(&self) -> RT40_41_R

Bits 8:9 - Rising trigger event configuration bit of Configurable Event input

impl R<u32, Reg<u32, _FTSR2>>

pub fn ft33(&self) -> FT33_R

Bit 1 - Falling trigger event configuration bit of Configurable Event input

pub fn ft40_41(&self) -> FT40_41_R

Bits 8:9 - Falling trigger event configuration bit of Configurable Event input

impl R<u32, Reg<u32, _SWIER2>>

pub fn swi33(&self) -> SWI33_R

Bit 1 - Software interrupt on event

pub fn swi40_41(&self) -> SWI40_41_R

Bits 8:9 - Software interrupt on event

impl R<u32, Reg<u32, _PR2>>

pub fn pif33(&self) -> PIF33_R

Bit 1 - Configurable event inputs x+32 Pending bit.

pub fn pif40_41(&self) -> PIF40_41_R

Bits 8:9 - Configurable event inputs x+32 Pending bit.

impl R<u32, Reg<u32, _IMR1>>

pub fn im(&self) -> IM_R

Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input

pub fn im0(&self) -> IM0_R

Bit 0 - CPU wakeup with interrupt mask on event input 0.

pub fn im1(&self) -> IM1_R

Bit 1 - CPU wakeup with interrupt mask on event input 1.

pub fn im2(&self) -> IM2_R

Bit 2 - CPU wakeup with interrupt mask on event input 2.

pub fn im3(&self) -> IM3_R

Bit 3 - CPU wakeup with interrupt mask on event input 3.

pub fn im4(&self) -> IM4_R

Bit 4 - CPU wakeup with interrupt mask on event input 4.

pub fn im5(&self) -> IM5_R

Bit 5 - CPU wakeup with interrupt mask on event input 5.

pub fn im6(&self) -> IM6_R

Bit 6 - CPU wakeup with interrupt mask on event input 6.

pub fn im7(&self) -> IM7_R

Bit 7 - CPU wakeup with interrupt mask on event input 7.

pub fn im8(&self) -> IM8_R

Bit 8 - CPU wakeup with interrupt mask on event input 8.

pub fn im9(&self) -> IM9_R

Bit 9 - CPU wakeup with interrupt mask on event input 9.

pub fn im10(&self) -> IM10_R

Bit 10 - CPU wakeup with interrupt mask on event input 10.

pub fn im11(&self) -> IM11_R

Bit 11 - CPU wakeup with interrupt mask on event input 11.

pub fn im12(&self) -> IM12_R

Bit 12 - CPU wakeup with interrupt mask on event input 12.

pub fn im13(&self) -> IM13_R

Bit 13 - CPU wakeup with interrupt mask on event input 13.

pub fn im14(&self) -> IM14_R

Bit 14 - CPU wakeup with interrupt mask on event input 14.

pub fn im15(&self) -> IM15_R

Bit 15 - CPU wakeup with interrupt mask on event input 15.

pub fn im16(&self) -> IM16_R

Bit 16 - CPU wakeup with interrupt mask on event input 16.

pub fn im17(&self) -> IM17_R

Bit 17 - CPU wakeup with interrupt mask on event input 17.

pub fn im18(&self) -> IM18_R

Bit 18 - CPU wakeup with interrupt mask on event input 18.

pub fn im19(&self) -> IM19_R

Bit 19 - CPU wakeup with interrupt mask on event input 19.

pub fn im20(&self) -> IM20_R

Bit 20 - CPU wakeup with interrupt mask on event input 20.

pub fn im21(&self) -> IM21_R

Bit 21 - CPU wakeup with interrupt mask on event input 21.

pub fn im22(&self) -> IM22_R

Bit 22 - CPU wakeup with interrupt mask on event input 22.

pub fn im23(&self) -> IM23_R

Bit 23 - CPU wakeup with interrupt mask on event input 23.

pub fn im24(&self) -> IM24_R

Bit 24 - CPU wakeup with interrupt mask on event input 24.

pub fn im25(&self) -> IM25_R

Bit 25 - CPU wakeup with interrupt mask on event input 25.

pub fn im26(&self) -> IM26_R

Bit 26 - CPU wakeup with interrupt mask on event input 26.

pub fn im27(&self) -> IM27_R

Bit 27 - CPU wakeup with interrupt mask on event input 27.

pub fn im28(&self) -> IM28_R

Bit 28 - CPU wakeup with interrupt mask on event input 28.

pub fn im29(&self) -> IM29_R

Bit 29 - CPU wakeup with interrupt mask on event input 29.

pub fn im30(&self) -> IM30_R

Bit 30 - CPU wakeup with interrupt mask on event input 30.

pub fn im31(&self) -> IM31_R

Bit 31 - CPU wakeup with interrupt mask on event input 31.

impl R<u32, Reg<u32, _C2IMR1>>

pub fn im(&self) -> IM_R

Bits 0:31 - CPU(m) wakeup with interrupt Mask on Event input

impl R<u32, Reg<u32, _C1EMR1>>

pub fn em0_15(&self) -> EM0_15_R

Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input

pub fn em17_21(&self) -> EM17_21_R

Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input

impl R<u32, Reg<u32, _C2EMR1>>

pub fn em0_15(&self) -> EM0_15_R

Bits 0:15 - CPU(m) Wakeup with event generation Mask on Event input

pub fn em17_21(&self) -> EM17_21_R

Bits 17:21 - CPU(m) Wakeup with event generation Mask on Event input

impl R<u32, Reg<u32, _C1IMR2>>

pub fn im(&self) -> IM_R

Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input

impl R<u32, Reg<u32, _C2IMR2>>

pub fn im(&self) -> IM_R

Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input

impl R<u32, Reg<u32, _C1EMR2>>

pub fn em(&self) -> EM_R

Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input

impl R<u32, Reg<u32, _C2EMR2>>

pub fn em(&self) -> EM_R

Bits 8:9 - CPU(m) Wakeup with event generation Mask on Event input

impl R<u32, Reg<u32, _HWCFGR5>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR6>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR7>>

pub fn cpuevent(&self) -> CPUEVENT_R

Bits 0:31 - HW configuration CPU event generation

impl R<u32, Reg<u32, _HWCFGR2>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR3>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR4>>

pub fn event_trg(&self) -> EVENT_TRG_R

Bits 0:31 - HW configuration event trigger type

impl R<u32, Reg<u32, _HWCFGR1>>

pub fn nbevents(&self) -> NBEVENTS_R

Bits 0:7 - HW configuration number of event

pub fn nbcpus(&self) -> NBCPUS_R

Bits 8:11 - HW configuration number of CPUs

pub fn cpuevten(&self) -> CPUEVTEN_R

Bits 12:15 - HW configuration of CPU(m) event output enable

impl R<u32, Reg<u32, _VERR>>

pub fn minrev(&self) -> MINREV_R

Bits 0:3 - Minor Revision number

pub fn majrev(&self) -> MAJREV_R

Bits 4:7 - Major Revision number

impl R<u32, Reg<u32, _IPIDR>>

pub fn ipid(&self) -> IPID_R

Bits 0:31 - IP Identification

impl R<u32, Reg<u32, _SIDR>>

pub fn sid(&self) -> SID_R

Bits 0:31 - Size Identification

impl R<u32, Reg<u32, _CR>>

pub fn syncokie(&self) -> SYNCOKIE_R

Bit 0 - SYNC event OK interrupt enable

pub fn syncwarnie(&self) -> SYNCWARNIE_R

Bit 1 - SYNC warning interrupt enable

pub fn errie(&self) -> ERRIE_R

Bit 2 - Synchronization or trimming error interrupt enable

pub fn esyncie(&self) -> ESYNCIE_R

Bit 3 - Expected SYNC interrupt enable

pub fn cen(&self) -> CEN_R

Bit 5 - Frequency error counter enable

pub fn autotrimen(&self) -> AUTOTRIMEN_R

Bit 6 - Automatic trimming enable

pub fn swsync(&self) -> SWSYNC_R

Bit 7 - Automatic trimming enable

pub fn trim(&self) -> TRIM_R

Bits 8:13 - HSI48 oscillator smooth trimming

impl R<u32, Reg<u32, _CFGR>>

pub fn reload(&self) -> RELOAD_R

Bits 0:15 - Counter reload value

pub fn felim(&self) -> FELIM_R

Bits 16:23 - Frequency error limit

pub fn syncdiv(&self) -> SYNCDIV_R

Bits 24:26 - SYNCDIV

pub fn syncsrc(&self) -> SYNCSRC_R

Bits 28:29 - SYNC signal source selection

pub fn syncpol(&self) -> SYNCPOL_R

Bit 31 - SYNC polarity selection

impl R<u32, Reg<u32, _ISR>>

pub fn syncokf(&self) -> SYNCOKF_R

Bit 0 - SYNC event OK flag

pub fn syncwarnf(&self) -> SYNCWARNF_R

Bit 1 - SYNC warning flag

pub fn errf(&self) -> ERRF_R

Bit 2 - Error flag

pub fn esyncf(&self) -> ESYNCF_R

Bit 3 - Expected SYNC flag

pub fn syncerr(&self) -> SYNCERR_R

Bit 8 - SYNC error

pub fn syncmiss(&self) -> SYNCMISS_R

Bit 9 - SYNC missed

pub fn trimovf(&self) -> TRIMOVF_R

Bit 10 - Trimming overflow or underflow

pub fn fedir(&self) -> FEDIR_R

Bit 15 - Frequency error direction

pub fn fecap(&self) -> FECAP_R

Bits 16:31 - Frequency error capture

impl R<u32, Reg<u32, _ICR>>

pub fn syncokc(&self) -> SYNCOKC_R

Bit 0 - SYNC event OK clear flag

pub fn syncwarnc(&self) -> SYNCWARNC_R

Bit 1 - warning clear flag

pub fn errc(&self) -> ERRC_R

Bit 2 - Error clear flag

pub fn esyncc(&self) -> ESYNCC_R

Bit 3 - Expected SYNC clear flag

impl R<u16, Reg<u16, _EP0R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP1R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP2R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP3R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP4R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP5R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP6R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _EP7R>>

pub fn ea(&self) -> EA_R

Bits 0:3 - Endpoint address

pub fn stat_tx(&self) -> STAT_TX_R

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&self) -> DTOG_TX_R

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&self) -> CTR_TX_R

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&self) -> EP_KIND_R

Bit 8 - Endpoint kind

pub fn ep_type(&self) -> EP_TYPE_R

Bits 9:10 - Endpoint type

pub fn setup(&self) -> SETUP_R

Bit 11 - Setup transaction completed

pub fn stat_rx(&self) -> STAT_RX_R

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&self) -> DTOG_RX_R

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&self) -> CTR_RX_R

Bit 15 - Correct transfer for reception

impl R<u16, Reg<u16, _CNTR>>

pub fn fres(&self) -> FRES_R

Bit 0 - Force USB Reset

pub fn pdwn(&self) -> PDWN_R

Bit 1 - Power down

pub fn lpmode(&self) -> LPMODE_R

Bit 2 - Low-power mode

pub fn fsusp(&self) -> FSUSP_R

Bit 3 - Force suspend

pub fn resume(&self) -> RESUME_R

Bit 4 - Resume request

pub fn l1resume(&self) -> L1RESUME_R

Bit 5 - LPM L1 Resume request

pub fn l1reqm(&self) -> L1REQM_R

Bit 7 - LPM L1 state request interrupt mask

pub fn esofm(&self) -> ESOFM_R

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&self) -> SOFM_R

Bit 9 - Start of frame interrupt mask

pub fn resetm(&self) -> RESETM_R

Bit 10 - USB reset interrupt mask

pub fn suspm(&self) -> SUSPM_R

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&self) -> WKUPM_R

Bit 12 - Wakeup interrupt mask

pub fn errm(&self) -> ERRM_R

Bit 13 - Error interrupt mask

pub fn pmaovrm(&self) -> PMAOVRM_R

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&self) -> CTRM_R

Bit 15 - Correct transfer interrupt mask

impl R<u16, Reg<u16, _ISTR>>

pub fn ep_id(&self) -> EP_ID_R

Bits 0:3 - Endpoint Identifier

pub fn dir(&self) -> DIR_R

Bit 4 - Direction of transaction

pub fn l1req(&self) -> L1REQ_R

Bit 7 - LPM L1 state request

pub fn esof(&self) -> ESOF_R

Bit 8 - Expected start frame

pub fn sof(&self) -> SOF_R

Bit 9 - start of frame

pub fn reset(&self) -> RESET_R

Bit 10 - reset request

pub fn susp(&self) -> SUSP_R

Bit 11 - Suspend mode request

pub fn wkup(&self) -> WKUP_R

Bit 12 - Wakeup

pub fn err(&self) -> ERR_R

Bit 13 - Error

pub fn pmaovr(&self) -> PMAOVR_R

Bit 14 - Packet memory area over / underrun

pub fn ctr(&self) -> CTR_R

Bit 15 - Correct transfer

impl R<u16, Reg<u16, _FNR>>

pub fn fn_(&self) -> FN_R

Bits 0:10 - Frame number

pub fn lsof(&self) -> LSOF_R

Bits 11:12 - Lost SOF

pub fn lck(&self) -> LCK_R

Bit 13 - Locked

pub fn rxdm(&self) -> RXDM_R

Bit 14 - Receive data - line status

pub fn rxdp(&self) -> RXDP_R

Bit 15 - Receive data + line status

impl R<u16, Reg<u16, _DADDR>>

pub fn add(&self) -> ADD_R

Bits 0:6 - Device address

pub fn ef(&self) -> EF_R

Bit 7 - Enable function

impl R<u16, Reg<u16, _BTABLE>>

pub fn btable(&self) -> BTABLE_R

Bits 3:15 - Buffer table

impl R<u16, Reg<u16, _COUNT0_TX>>

pub fn count0_tx(&self) -> COUNT0_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT1_TX>>

pub fn count1_tx(&self) -> COUNT1_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT2_TX>>

pub fn count2_tx(&self) -> COUNT2_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT3_TX>>

pub fn count3_tx(&self) -> COUNT3_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT4_TX>>

pub fn count4_tx(&self) -> COUNT4_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT5_TX>>

pub fn count5_tx(&self) -> COUNT5_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT6_TX>>

pub fn count6_tx(&self) -> COUNT6_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _COUNT7_TX>>

pub fn count7_tx(&self) -> COUNT7_TX_R

Bits 0:9 - Transmission byte count

impl R<u16, Reg<u16, _ADDR0_RX>>

pub fn addr0_rx(&self) -> ADDR0_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR1_RX>>

pub fn addr1_rx(&self) -> ADDR1_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR2_RX>>

pub fn addr2_rx(&self) -> ADDR2_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR3_RX>>

pub fn addr3_rx(&self) -> ADDR3_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR4_RX>>

pub fn addr4_rx(&self) -> ADDR4_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR5_RX>>

pub fn addr5_rx(&self) -> ADDR5_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR6_RX>>

pub fn addr6_rx(&self) -> ADDR6_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _ADDR7_RX>>

pub fn addr7_rx(&self) -> ADDR7_RX_R

Bits 1:15 - Reception buffer address

impl R<u16, Reg<u16, _COUNT0_RX>>

pub fn count0_rx(&self) -> COUNT0_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT1_RX>>

pub fn count1_rx(&self) -> COUNT1_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT2_RX>>

pub fn count2_rx(&self) -> COUNT2_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT3_RX>>

pub fn count3_rx(&self) -> COUNT3_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT4_RX>>

pub fn count4_rx(&self) -> COUNT4_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT5_RX>>

pub fn count5_rx(&self) -> COUNT5_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT6_RX>>

pub fn count6_rx(&self) -> COUNT6_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _COUNT7_RX>>

pub fn count7_rx(&self) -> COUNT7_RX_R

Bits 0:9 - Reception byte count

pub fn num_block(&self) -> NUM_BLOCK_R

Bits 10:14 - Number of blocks

pub fn bl_size(&self) -> BL_SIZE_R

Bit 15 - Block size

impl R<u16, Reg<u16, _LPMCSR>>

pub fn lpmen(&self) -> LPMEN_R

Bit 0 - LPM support enable

pub fn lpmack(&self) -> LPMACK_R

Bit 1 - LPM Token acknowledge enable

pub fn remwake(&self) -> REMWAKE_R

Bit 3 - RemoteWake value

pub fn besl(&self) -> BESL_R

Bits 4:7 - BESL value

impl R<u16, Reg<u16, _BCDR>>

pub fn bcden(&self) -> BCDEN_R

Bit 0 - Battery charging detector (BCD) enable

pub fn dcden(&self) -> DCDEN_R

Bit 1 - Data contact detection (DCD) mode enable

pub fn pden(&self) -> PDEN_R

Bit 2 - Primary detection (PD) mode enable

pub fn sden(&self) -> SDEN_R

Bit 3 - Secondary detection (SD) mode enable

pub fn dcdet(&self) -> DCDET_R

Bit 4 - Data contact detection (DCD) status

pub fn pdet(&self) -> PDET_R

Bit 5 - Primary detection (PD) status

pub fn sdet(&self) -> SDET_R

Bit 6 - Secondary detection (SD) status

pub fn ps2det(&self) -> PS2DET_R

Bit 7 - DM pull-up detection status

pub fn dppu(&self) -> DPPU_R

Bit 15 - DP pull-up control

impl R<u32, Reg<u32, _CTRL>>

pub fn enable(&self) -> ENABLE_R

Bit 0 - Counter enable

pub fn tickint(&self) -> TICKINT_R

Bit 1 - SysTick exception request enable

pub fn clksource(&self) -> CLKSOURCE_R

Bit 2 - Clock source selection

pub fn countflag(&self) -> COUNTFLAG_R

Bit 16 - COUNTFLAG

impl R<u32, Reg<u32, _LOAD>>

pub fn reload(&self) -> RELOAD_R

Bits 0:23 - RELOAD value

impl R<u32, Reg<u32, _VAL>>

pub fn current(&self) -> CURRENT_R

Bits 0:23 - Current counter value

impl R<u32, Reg<u32, _CALIB>>

pub fn tenms(&self) -> TENMS_R

Bits 0:23 - Calibration value

pub fn skew(&self) -> SKEW_R

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&self) -> NOREF_R

Bit 31 - NOREF flag. Reads as zero

impl R<u32, Reg<u32, _STIR>>

pub fn intid(&self) -> INTID_R

Bits 0:8 - Software generated interrupt ID

impl R<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&self) -> DISMCYCINT_R

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&self) -> DISDEFWBUF_R

Bit 1 - DISDEFWBUF

pub fn disfold(&self) -> DISFOLD_R

Bit 2 - DISFOLD

pub fn disfpca(&self) -> DISFPCA_R

Bit 8 - DISFPCA

pub fn disoofp(&self) -> DISOOFP_R

Bit 9 - DISOOFP

impl R<u32, Reg<u32, _CPACR>>

pub fn cp(&self) -> CP_R

Bits 20:23 - CP

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T>

where U: PartialEq, FI: Copy + Into<U>,

fn eq(&self, other: &FI) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.