Expand description
Universal serial bus full-speed device interface
Modules§
- addr0_
rx - Reception buffer address 0
- addr1_
rx - Reception buffer address 0
- addr2_
rx - Reception buffer address 0
- addr3_
rx - Reception buffer address 0
- addr4_
rx - Reception buffer address 0
- addr5_
rx - Reception buffer address 0
- addr6_
rx - Reception buffer address 0
- addr7_
rx - Reception buffer address 0
- bcdr
- Battery charging detector(
- btable
- Buffer table address
- cntr
- control register
- count0_
rx - Reception byte count 0
- count0_
tx - Transmission byte count 0
- count1_
rx - Reception byte count 0
- count1_
tx - Transmission byte count 0
- count2_
rx - Reception byte count 0
- count2_
tx - Transmission byte count 0
- count3_
rx - Reception byte count 0
- count3_
tx - Transmission byte count 0
- count4_
rx - Reception byte count 0
- count4_
tx - Transmission byte count 0
- count5_
rx - Reception byte count 0
- count5_
tx - Transmission byte count 0
- count6_
rx - Reception byte count 0
- count6_
tx - Transmission byte count 0
- count7_
rx - Reception byte count 0
- count7_
tx - Transmission byte count 0
- daddr
- device address
- ep0r
- endpoint 0 register
- ep1r
- endpoint 1 register
- ep2r
- endpoint 2 register
- ep3r
- endpoint 3 register
- ep4r
- endpoint 4 register
- ep5r
- endpoint 5 register
- ep6r
- endpoint 6 register
- ep7r
- endpoint 7 register
- fnr
- frame number register
- istr
- interrupt status register
- lpmcsr
- control and status register
Structs§
- Register
Block - Register block
Type Aliases§
- ADDR0_
RX - Reception buffer address 0
- ADDR1_
RX - Reception buffer address 0
- ADDR2_
RX - Reception buffer address 0
- ADDR3_
RX - Reception buffer address 0
- ADDR4_
RX - Reception buffer address 0
- ADDR5_
RX - Reception buffer address 0
- ADDR6_
RX - Reception buffer address 0
- ADDR7_
RX - Reception buffer address 0
- BCDR
- Battery charging detector(
- BTABLE
- Buffer table address
- CNTR
- control register
- COUN
T0_ RX - Reception byte count 0
- COUN
T0_ TX - Transmission byte count 0
- COUN
T1_ RX - Reception byte count 0
- COUN
T1_ TX - Transmission byte count 0
- COUN
T2_ RX - Reception byte count 0
- COUN
T2_ TX - Transmission byte count 0
- COUN
T3_ RX - Reception byte count 0
- COUN
T3_ TX - Transmission byte count 0
- COUN
T4_ RX - Reception byte count 0
- COUN
T4_ TX - Transmission byte count 0
- COUN
T5_ RX - Reception byte count 0
- COUN
T5_ TX - Transmission byte count 0
- COUN
T6_ RX - Reception byte count 0
- COUN
T6_ TX - Transmission byte count 0
- COUN
T7_ RX - Reception byte count 0
- COUN
T7_ TX - Transmission byte count 0
- DADDR
- device address
- EP0R
- endpoint 0 register
- EP1R
- endpoint 1 register
- EP2R
- endpoint 2 register
- EP3R
- endpoint 3 register
- EP4R
- endpoint 4 register
- EP5R
- endpoint 5 register
- EP6R
- endpoint 6 register
- EP7R
- endpoint 7 register
- FNR
- frame number register
- ISTR
- interrupt status register
- LPMCSR
- control and status register