1#[doc = "Reader of register CR"]
2pub type R = crate::R<u32, super::CR>;
3#[doc = "Writer for register CR"]
4pub type W = crate::W<u32, super::CR>;
5#[doc = "Register CR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `BIAS`"]
14pub type BIAS_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `BIAS`"]
16pub struct BIAS_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> BIAS_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
24 self.w
25 }
26}
27#[doc = "Reader of field `DUTY`"]
28pub type DUTY_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `DUTY`"]
30pub struct DUTY_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> DUTY_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2);
38 self.w
39 }
40}
41#[doc = "Reader of field `VSEL`"]
42pub type VSEL_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `VSEL`"]
44pub struct VSEL_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> VSEL_W<'a> {
48 #[doc = r"Sets the field bit"]
49 #[inline(always)]
50 pub fn set_bit(self) -> &'a mut W {
51 self.bit(true)
52 }
53 #[doc = r"Clears the field bit"]
54 #[inline(always)]
55 pub fn clear_bit(self) -> &'a mut W {
56 self.bit(false)
57 }
58 #[doc = r"Writes raw bits to the field"]
59 #[inline(always)]
60 pub fn bit(self, value: bool) -> &'a mut W {
61 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
62 self.w
63 }
64}
65#[doc = "Reader of field `LCDEN`"]
66pub type LCDEN_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `LCDEN`"]
68pub struct LCDEN_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> LCDEN_W<'a> {
72 #[doc = r"Sets the field bit"]
73 #[inline(always)]
74 pub fn set_bit(self) -> &'a mut W {
75 self.bit(true)
76 }
77 #[doc = r"Clears the field bit"]
78 #[inline(always)]
79 pub fn clear_bit(self) -> &'a mut W {
80 self.bit(false)
81 }
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub fn bit(self, value: bool) -> &'a mut W {
85 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
86 self.w
87 }
88}
89#[doc = "Reader of field `MUX_SEG`"]
90pub type MUX_SEG_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `MUX_SEG`"]
92pub struct MUX_SEG_W<'a> {
93 w: &'a mut W,
94}
95impl<'a> MUX_SEG_W<'a> {
96 #[doc = r"Sets the field bit"]
97 #[inline(always)]
98 pub fn set_bit(self) -> &'a mut W {
99 self.bit(true)
100 }
101 #[doc = r"Clears the field bit"]
102 #[inline(always)]
103 pub fn clear_bit(self) -> &'a mut W {
104 self.bit(false)
105 }
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub fn bit(self, value: bool) -> &'a mut W {
109 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
110 self.w
111 }
112}
113#[doc = "Reader of field `BUFEN`"]
114pub type BUFEN_R = crate::R<bool, bool>;
115#[doc = "Write proxy for field `BUFEN`"]
116pub struct BUFEN_W<'a> {
117 w: &'a mut W,
118}
119impl<'a> BUFEN_W<'a> {
120 #[doc = r"Sets the field bit"]
121 #[inline(always)]
122 pub fn set_bit(self) -> &'a mut W {
123 self.bit(true)
124 }
125 #[doc = r"Clears the field bit"]
126 #[inline(always)]
127 pub fn clear_bit(self) -> &'a mut W {
128 self.bit(false)
129 }
130 #[doc = r"Writes raw bits to the field"]
131 #[inline(always)]
132 pub fn bit(self, value: bool) -> &'a mut W {
133 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
134 self.w
135 }
136}
137impl R {
138 #[doc = "Bits 5:6 - Bias selector"]
139 #[inline(always)]
140 pub fn bias(&self) -> BIAS_R {
141 BIAS_R::new(((self.bits >> 5) & 0x03) as u8)
142 }
143 #[doc = "Bits 2:4 - Duty selection"]
144 #[inline(always)]
145 pub fn duty(&self) -> DUTY_R {
146 DUTY_R::new(((self.bits >> 2) & 0x07) as u8)
147 }
148 #[doc = "Bit 1 - Voltage source selection"]
149 #[inline(always)]
150 pub fn vsel(&self) -> VSEL_R {
151 VSEL_R::new(((self.bits >> 1) & 0x01) != 0)
152 }
153 #[doc = "Bit 0 - LCD controller enable"]
154 #[inline(always)]
155 pub fn lcden(&self) -> LCDEN_R {
156 LCDEN_R::new((self.bits & 0x01) != 0)
157 }
158 #[doc = "Bit 7 - Mux segment enable"]
159 #[inline(always)]
160 pub fn mux_seg(&self) -> MUX_SEG_R {
161 MUX_SEG_R::new(((self.bits >> 7) & 0x01) != 0)
162 }
163 #[doc = "Bit 8 - Voltage output buffer enable"]
164 #[inline(always)]
165 pub fn bufen(&self) -> BUFEN_R {
166 BUFEN_R::new(((self.bits >> 8) & 0x01) != 0)
167 }
168}
169impl W {
170 #[doc = "Bits 5:6 - Bias selector"]
171 #[inline(always)]
172 pub fn bias(&mut self) -> BIAS_W {
173 BIAS_W { w: self }
174 }
175 #[doc = "Bits 2:4 - Duty selection"]
176 #[inline(always)]
177 pub fn duty(&mut self) -> DUTY_W {
178 DUTY_W { w: self }
179 }
180 #[doc = "Bit 1 - Voltage source selection"]
181 #[inline(always)]
182 pub fn vsel(&mut self) -> VSEL_W {
183 VSEL_W { w: self }
184 }
185 #[doc = "Bit 0 - LCD controller enable"]
186 #[inline(always)]
187 pub fn lcden(&mut self) -> LCDEN_W {
188 LCDEN_W { w: self }
189 }
190 #[doc = "Bit 7 - Mux segment enable"]
191 #[inline(always)]
192 pub fn mux_seg(&mut self) -> MUX_SEG_W {
193 MUX_SEG_W { w: self }
194 }
195 #[doc = "Bit 8 - Voltage output buffer enable"]
196 #[inline(always)]
197 pub fn bufen(&mut self) -> BUFEN_W {
198 BUFEN_W { w: self }
199 }
200}