Struct stm32ral::stm32wb::stm32wb55::rcc::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock {
Show 48 fields pub CR: RWRegister<u32>, pub ICSCR: RWRegister<u32>, pub CFGR: RWRegister<u32>, pub PLLCFGR: RWRegister<u32>, pub PLLSAI1CFGR: RWRegister<u32>, pub CIER: RWRegister<u32>, pub CIFR: RORegister<u32>, pub CICR: WORegister<u32>, pub SMPSCR: RWRegister<u32>, pub AHB1RSTR: RWRegister<u32>, pub AHB2RSTR: RWRegister<u32>, pub AHB3RSTR: RWRegister<u32>, pub APB1RSTR1: RWRegister<u32>, pub APB1RSTR2: RWRegister<u32>, pub APB2RSTR: RWRegister<u32>, pub APB3RSTR: RWRegister<u32>, pub AHB1ENR: RWRegister<u32>, pub AHB2ENR: RWRegister<u32>, pub AHB3ENR: RWRegister<u32>, pub APB1ENR1: RWRegister<u32>, pub APB1ENR2: RWRegister<u32>, pub APB2ENR: RWRegister<u32>, pub AHB1SMENR: RWRegister<u32>, pub AHB2SMENR: RWRegister<u32>, pub AHB3SMENR: RWRegister<u32>, pub APB1SMENR1: RWRegister<u32>, pub APB1SMENR2: RWRegister<u32>, pub APB2SMENR: RWRegister<u32>, pub CCIPR: RWRegister<u32>, pub BDCR: RWRegister<u32>, pub CSR: RWRegister<u32>, pub CRRCR: RWRegister<u32>, pub HSECR: RWRegister<u32>, pub EXTCFGR: RWRegister<u32>, pub C2AHB1ENR: RWRegister<u32>, pub C2AHB2ENR: RWRegister<u32>, pub C2AHB3ENR: RWRegister<u32>, pub C2APB1ENR1: RWRegister<u32>, pub C2APB1ENR2: RWRegister<u32>, pub C2APB2ENR: RWRegister<u32>, pub C2APB3ENR: RWRegister<u32>, pub C2AHB1SMENR: RWRegister<u32>, pub C2AHB2SMENR: RWRegister<u32>, pub C2AHB3SMENR: RWRegister<u32>, pub C2APB1SMENR1: RWRegister<u32>, pub C2APB1SMENR2: RWRegister<u32>, pub C2APB2SMENR: RWRegister<u32>, pub C2APB3SMENR: RWRegister<u32>, // some fields omitted
}

Fields

CR: RWRegister<u32>

Clock control register

ICSCR: RWRegister<u32>

Internal clock sources calibration register

CFGR: RWRegister<u32>

Clock configuration register

PLLCFGR: RWRegister<u32>

PLLSYS configuration register

PLLSAI1CFGR: RWRegister<u32>

PLLSAI1 configuration register

CIER: RWRegister<u32>

Clock interrupt enable register

CIFR: RORegister<u32>

Clock interrupt flag register

CICR: WORegister<u32>

Clock interrupt clear register

SMPSCR: RWRegister<u32>

Step Down converter control register

AHB1RSTR: RWRegister<u32>

AHB1 peripheral reset register

AHB2RSTR: RWRegister<u32>

AHB2 peripheral reset register

AHB3RSTR: RWRegister<u32>

AHB3 peripheral reset register

APB1RSTR1: RWRegister<u32>

APB1 peripheral reset register 1

APB1RSTR2: RWRegister<u32>

APB1 peripheral reset register 2

APB2RSTR: RWRegister<u32>

APB2 peripheral reset register

APB3RSTR: RWRegister<u32>

APB3 peripheral reset register

AHB1ENR: RWRegister<u32>

AHB1 peripheral clock enable register

AHB2ENR: RWRegister<u32>

AHB2 peripheral clock enable register

AHB3ENR: RWRegister<u32>

AHB3 peripheral clock enable register

APB1ENR1: RWRegister<u32>

APB1ENR1

APB1ENR2: RWRegister<u32>

APB1 peripheral clock enable register 2

APB2ENR: RWRegister<u32>

APB2ENR

AHB1SMENR: RWRegister<u32>

AHB1 peripheral clocks enable in Sleep and Stop modes register

AHB2SMENR: RWRegister<u32>

AHB2 peripheral clocks enable in Sleep and Stop modes register

AHB3SMENR: RWRegister<u32>

AHB3 peripheral clocks enable in Sleep and Stop modes register

APB1SMENR1: RWRegister<u32>

APB1SMENR1

APB1SMENR2: RWRegister<u32>

APB1 peripheral clocks enable in Sleep and Stop modes register 2

APB2SMENR: RWRegister<u32>

APB2SMENR

CCIPR: RWRegister<u32>

CCIPR

BDCR: RWRegister<u32>

BDCR

CSR: RWRegister<u32>

CSR

CRRCR: RWRegister<u32>

Clock recovery RC register

HSECR: RWRegister<u32>

Clock HSE register

EXTCFGR: RWRegister<u32>

Extended clock recovery register

C2AHB1ENR: RWRegister<u32>

CPU2 AHB1 peripheral clock enable register

C2AHB2ENR: RWRegister<u32>

CPU2 AHB2 peripheral clock enable register

C2AHB3ENR: RWRegister<u32>

CPU2 AHB3 peripheral clock enable register

C2APB1ENR1: RWRegister<u32>

CPU2 APB1ENR1

C2APB1ENR2: RWRegister<u32>

CPU2 APB1 peripheral clock enable register 2

C2APB2ENR: RWRegister<u32>

CPU2 APB2ENR

C2APB3ENR: RWRegister<u32>

CPU2 APB3ENR

C2AHB1SMENR: RWRegister<u32>

CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register

C2AHB2SMENR: RWRegister<u32>

CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register

C2AHB3SMENR: RWRegister<u32>

CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register

C2APB1SMENR1: RWRegister<u32>

CPU2 APB1SMENR1

C2APB1SMENR2: RWRegister<u32>

CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2

C2APB2SMENR: RWRegister<u32>

CPU2 APB2SMENR

C2APB3SMENR: RWRegister<u32>

CPU2 APB3SMENR

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Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.