Struct stm32ral::stm32wb::stm32wb55::hsem::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 79 fields
pub R0: RWRegister<u32>,
pub R1: RWRegister<u32>,
pub R2: RWRegister<u32>,
pub R3: RWRegister<u32>,
pub R4: RWRegister<u32>,
pub R5: RWRegister<u32>,
pub R6: RWRegister<u32>,
pub R7: RWRegister<u32>,
pub R8: RWRegister<u32>,
pub R9: RWRegister<u32>,
pub R10: RWRegister<u32>,
pub R11: RWRegister<u32>,
pub R12: RWRegister<u32>,
pub R13: RWRegister<u32>,
pub R14: RWRegister<u32>,
pub R15: RWRegister<u32>,
pub R16: RWRegister<u32>,
pub R17: RWRegister<u32>,
pub R18: RWRegister<u32>,
pub R19: RWRegister<u32>,
pub R20: RWRegister<u32>,
pub R21: RWRegister<u32>,
pub R22: RWRegister<u32>,
pub R23: RWRegister<u32>,
pub R24: RWRegister<u32>,
pub R25: RWRegister<u32>,
pub R26: RWRegister<u32>,
pub R27: RWRegister<u32>,
pub R28: RWRegister<u32>,
pub R29: RWRegister<u32>,
pub R30: RWRegister<u32>,
pub R31: RWRegister<u32>,
pub RLR0: RORegister<u32>,
pub RLR1: RORegister<u32>,
pub RLR2: RORegister<u32>,
pub RLR3: RORegister<u32>,
pub RLR4: RORegister<u32>,
pub RLR5: RORegister<u32>,
pub RLR6: RORegister<u32>,
pub RLR7: RORegister<u32>,
pub RLR8: RORegister<u32>,
pub RLR9: RORegister<u32>,
pub RLR10: RORegister<u32>,
pub RLR11: RORegister<u32>,
pub RLR12: RORegister<u32>,
pub RLR13: RORegister<u32>,
pub RLR14: RORegister<u32>,
pub RLR15: RORegister<u32>,
pub RLR16: RORegister<u32>,
pub RLR17: RORegister<u32>,
pub RLR18: RORegister<u32>,
pub RLR19: RORegister<u32>,
pub RLR20: RORegister<u32>,
pub RLR21: RORegister<u32>,
pub RLR22: RORegister<u32>,
pub RLR23: RORegister<u32>,
pub RLR24: RORegister<u32>,
pub RLR25: RORegister<u32>,
pub RLR26: RORegister<u32>,
pub RLR27: RORegister<u32>,
pub RLR28: RORegister<u32>,
pub RLR29: RORegister<u32>,
pub RLR30: RORegister<u32>,
pub RLR31: RORegister<u32>,
pub C1IER: RWRegister<u32>,
pub C1ICR: RWRegister<u32>,
pub C1ISR: RORegister<u32>,
pub C1MISR: RORegister<u32>,
pub C2IER: RWRegister<u32>,
pub C2ICR: RWRegister<u32>,
pub C2ISR: RORegister<u32>,
pub C2MISR: RORegister<u32>,
pub CR: RWRegister<u32>,
pub KEYR: RWRegister<u32>,
pub HWCFGR2: RORegister<u32>,
pub HWCFGR1: RORegister<u32>,
pub VERR: RORegister<u32>,
pub IPIDR: RORegister<u32>,
pub SIDR: RORegister<u32>,
// some fields omitted
}
Fields
R0: RWRegister<u32>
Semaphore 0 register
R1: RWRegister<u32>
Semaphore 1 register
R2: RWRegister<u32>
Semaphore 2 register
R3: RWRegister<u32>
Semaphore 3 register
R4: RWRegister<u32>
Semaphore 4 register
R5: RWRegister<u32>
Semaphore 5 register
R6: RWRegister<u32>
Semaphore 6 register
R7: RWRegister<u32>
Semaphore 7 register
R8: RWRegister<u32>
Semaphore 8 register
R9: RWRegister<u32>
Semaphore 9 register
R10: RWRegister<u32>
Semaphore 10 register
R11: RWRegister<u32>
Semaphore 11 register
R12: RWRegister<u32>
Semaphore 12 register
R13: RWRegister<u32>
Semaphore 13 register
R14: RWRegister<u32>
Semaphore 14 register
R15: RWRegister<u32>
Semaphore 15 register
R16: RWRegister<u32>
Semaphore 16 register
R17: RWRegister<u32>
Semaphore 17 register
R18: RWRegister<u32>
Semaphore 18 register
R19: RWRegister<u32>
Semaphore 19 register
R20: RWRegister<u32>
Semaphore 20 register
R21: RWRegister<u32>
Semaphore 21 register
R22: RWRegister<u32>
Semaphore 22 register
R23: RWRegister<u32>
Semaphore 23 register
R24: RWRegister<u32>
Semaphore 24 register
R25: RWRegister<u32>
Semaphore 25 register
R26: RWRegister<u32>
Semaphore 26 register
R27: RWRegister<u32>
Semaphore 27 register
R28: RWRegister<u32>
Semaphore 28 register
R29: RWRegister<u32>
Semaphore 29 register
R30: RWRegister<u32>
Semaphore 30 register
R31: RWRegister<u32>
Semaphore 31 register
RLR0: RORegister<u32>
Semaphore 0 read lock register
RLR1: RORegister<u32>
Semaphore 1 read lock register
RLR2: RORegister<u32>
Semaphore 2 read lock register
RLR3: RORegister<u32>
Semaphore 3 read lock register
RLR4: RORegister<u32>
Semaphore 4 read lock read lock register
RLR5: RORegister<u32>
Semaphore 5 read lock register
RLR6: RORegister<u32>
Semaphore 6 read lock register
RLR7: RORegister<u32>
Semaphore 7 read lock register
RLR8: RORegister<u32>
Semaphore 8 read lock register
RLR9: RORegister<u32>
Semaphore 9 read lock register
RLR10: RORegister<u32>
Semaphore 10 read lock register
RLR11: RORegister<u32>
Semaphore 11 read lock register
RLR12: RORegister<u32>
Semaphore 12 read lock register
RLR13: RORegister<u32>
Semaphore 13 read lock register
RLR14: RORegister<u32>
Semaphore 14 read lock register
RLR15: RORegister<u32>
Semaphore 15 read lock register
RLR16: RORegister<u32>
Semaphore 16 read lock register
RLR17: RORegister<u32>
Semaphore 17 read lock register
RLR18: RORegister<u32>
Semaphore 18 read lock register
RLR19: RORegister<u32>
Semaphore 19 read lock register
RLR20: RORegister<u32>
Semaphore 20 read lock register
RLR21: RORegister<u32>
Semaphore 21 read lock register
RLR22: RORegister<u32>
Semaphore 22 read lock register
RLR23: RORegister<u32>
Semaphore 23 read lock register
RLR24: RORegister<u32>
Semaphore 24 read lock register
RLR25: RORegister<u32>
Semaphore 25 read lock register
RLR26: RORegister<u32>
Semaphore 26 read lock register
RLR27: RORegister<u32>
Semaphore 27 read lock register
RLR28: RORegister<u32>
Semaphore 28 read lock register
RLR29: RORegister<u32>
Semaphore 29 read lock register
RLR30: RORegister<u32>
Semaphore 30 read lock register
RLR31: RORegister<u32>
Semaphore 31 read lock register
C1IER: RWRegister<u32>
HSEM Interrupt enable register
C1ICR: RWRegister<u32>
HSEM Interrupt clear register
C1ISR: RORegister<u32>
HSEM Interrupt status register
C1MISR: RORegister<u32>
HSEM Masked interrupt status register
C2IER: RWRegister<u32>
HSEM Interrupt enable register
C2ICR: RWRegister<u32>
HSEM Interrupt clear register
C2ISR: RORegister<u32>
HSEM Interrupt status register
C2MISR: RORegister<u32>
HSEM Masked interrupt status register
CR: RWRegister<u32>
Semaphore Clear register
KEYR: RWRegister<u32>
Interrupt clear register
HWCFGR2: RORegister<u32>
Semaphore hardware configuration register 2
HWCFGR1: RORegister<u32>
Semaphore hardware configuration register 1
VERR: RORegister<u32>
HSEM version register
IPIDR: RORegister<u32>
HSEM indentification register
SIDR: RORegister<u32>
HSEM size indentification register