Struct stm32ral::stm32mp::peripherals::tim8::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {Show 26 fields
    pub TIM8_CR1: RWRegister<u16>,
    pub TIM8_CR2: RWRegister<u32>,
    pub TIM8_SMCR: RWRegister<u32>,
    pub TIM8_DIER: RWRegister<u16>,
    pub TIM8_SR: RWRegister<u32>,
    pub TIM8_EGR: WORegister<u16>,
    pub TIM8_CCMR1ALTERNATE8: RWRegister<u32>,
    pub TIM8_CCMR2ALTERNATE24: RWRegister<u32>,
    pub TIM8_CCER: RWRegister<u32>,
    pub TIM8_CNT: RWRegister<u32>,
    pub TIM8_PSC: RWRegister<u16>,
    pub TIM8_ARR: RWRegister<u16>,
    pub TIM8_RCR: RWRegister<u16>,
    pub TIM8_CCR1: RWRegister<u16>,
    pub TIM8_CCR2: RWRegister<u16>,
    pub TIM8_CCR3: RWRegister<u16>,
    pub TIM8_CCR4: RWRegister<u16>,
    pub TIM8_BDTR: RWRegister<u32>,
    pub TIM8_DCR: RWRegister<u16>,
    pub TIM8_DMAR: RWRegister<u32>,
    pub TIM8_CCMR3: RWRegister<u32>,
    pub TIM8_CCR5: RWRegister<u32>,
    pub TIM8_CCR6: RWRegister<u16>,
    pub TIM8_AF1: RWRegister<u32>,
    pub TIM8_AF2: RWRegister<u32>,
    pub TIM8_TISEL: RWRegister<u32>,
    // some fields omitted
}

Fields

TIM8_CR1: RWRegister<u16>

TIM8 control register 1

TIM8_CR2: RWRegister<u32>

TIM8 control register 2

TIM8_SMCR: RWRegister<u32>

TIM8 slave mode control register

TIM8_DIER: RWRegister<u16>

TIM8 DMA/interrupt enable register

TIM8_SR: RWRegister<u32>

TIM8 status register

TIM8_EGR: WORegister<u16>

TIM8 event generation register

TIM8_CCMR1ALTERNATE8: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM8_CCMR2ALTERNATE24: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM8_CCER: RWRegister<u32>

TIM8 capture/compare enable register

TIM8_CNT: RWRegister<u32>

TIM8 counter

TIM8_PSC: RWRegister<u16>

TIM8 prescaler

TIM8_ARR: RWRegister<u16>

TIM8 auto-reload register

TIM8_RCR: RWRegister<u16>

TIM8 repetition counter register

TIM8_CCR1: RWRegister<u16>

TIM8 capture/compare register 1

TIM8_CCR2: RWRegister<u16>

TIM8 capture/compare register 2

TIM8_CCR3: RWRegister<u16>

TIM8 capture/compare register 3

TIM8_CCR4: RWRegister<u16>

TIM8 capture/compare register 4

TIM8_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM8_DCR: RWRegister<u16>

TIM8 DMA control register

TIM8_DMAR: RWRegister<u32>

TIM8 DMA address for full transfer

TIM8_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM8_CCR5: RWRegister<u32>

TIM8 capture/compare register 5

TIM8_CCR6: RWRegister<u16>

TIM8 capture/compare register 6

TIM8_AF1: RWRegister<u32>

TIM8 Alternate function option register 1