Struct stm32ral::stm32mp::peripherals::tim3::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIM3_CR1: RWRegister<u16>,
    pub TIM3_CR2: RWRegister<u32>,
    pub TIM3_SMCR: RWRegister<u32>,
    pub TIM3_DIER: RWRegister<u16>,
    pub TIM3_SR: RWRegister<u32>,
    pub TIM3_EGR: WORegister<u16>,
    pub TIM3_CCMR1ALTERNATE3: RWRegister<u32>,
    pub TIM3_CCMR2ALTERNATE19: RWRegister<u32>,
    pub TIM3_CCER: RWRegister<u32>,
    pub TIM3_CNT: RWRegister<u32>,
    pub TIM3_PSC: RWRegister<u16>,
    pub TIM3_ARR: RWRegister<u16>,
    pub TIM3_RCR: RWRegister<u16>,
    pub TIM3_CCR1: RWRegister<u16>,
    pub TIM3_CCR2: RWRegister<u16>,
    pub TIM3_CCR3: RWRegister<u16>,
    pub TIM3_CCR4: RWRegister<u16>,
    pub TIM3_BDTR: RWRegister<u32>,
    pub TIM3_DCR: RWRegister<u16>,
    pub TIM3_DMAR: RWRegister<u32>,
    pub TIM3_CCMR3: RWRegister<u32>,
    pub TIM3_CCR5: RWRegister<u32>,
    pub TIM3_CCR6: RWRegister<u16>,
    // some fields omitted
}

Fields

TIM3_CR1: RWRegister<u16>

TIM3 control register 1

TIM3_CR2: RWRegister<u32>

TIM3 control register 2

TIM3_SMCR: RWRegister<u32>

TIM3 slave mode control register

TIM3_DIER: RWRegister<u16>

TIM3 DMA/interrupt enable register

TIM3_SR: RWRegister<u32>

TIM3 status register

TIM3_EGR: WORegister<u16>

TIM3 event generation register

TIM3_CCMR1ALTERNATE3: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM3_CCMR2ALTERNATE19: RWRegister<u32>

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

TIM3_CCER: RWRegister<u32>

TIM3 capture/compare enable register

TIM3_CNT: RWRegister<u32>

TIM3 counter

TIM3_PSC: RWRegister<u16>

TIM3 prescaler

TIM3_ARR: RWRegister<u16>

TIM3 auto-reload register

TIM3_RCR: RWRegister<u16>

TIM3 repetition counter register

TIM3_CCR1: RWRegister<u16>

TIM3 capture/compare register 1

TIM3_CCR2: RWRegister<u16>

TIM3 capture/compare register 2

TIM3_CCR3: RWRegister<u16>

TIM3 capture/compare register 3

TIM3_CCR4: RWRegister<u16>

TIM3 capture/compare register 4

TIM3_BDTR: RWRegister<u32>

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIM3_DCR: RWRegister<u16>

TIM3 DMA control register

TIM3_DMAR: RWRegister<u32>

TIM3 DMA address for full transfer

TIM3_CCMR3: RWRegister<u32>

The channels 5 and 6 can only be configured in output. Output compare mode:

TIM3_CCR5: RWRegister<u32>

TIM3 capture/compare register 5

TIM3_CCR6: RWRegister<u16>

TIM3 capture/compare register 6