Struct stm32ral::stm32mp::peripherals::tim16::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub TIMx_CR1: RWRegister<u16>,
    pub TIMx_CR2: RWRegister<u16>,
    pub TIMx_DIER: RWRegister<u16>,
    pub TIMx_SR: RWRegister<u16>,
    pub TIMx_EGR: WORegister<u32>,
    pub TIMx_CCER: RWRegister<u16>,
    pub TIMx_CNT: RWRegister<u32>,
    pub TIMx_PSC: RWRegister<u16>,
    pub TIMx_ARR: RWRegister<u16>,
    pub TIMx_RCR: RWRegister<u16>,
    pub TIMx_CCR1: RWRegister<u16>,
    pub TIMx_BDTR: RWRegister<u32>,
    pub TIMx_DCR: RWRegister<u16>,
    pub TIMx_DMAR: RWRegister<u16>,
    pub TIMx_AF1: RWRegister<u32>,
    pub TIMx_TISEL: RWRegister<u32>,
    // some fields omitted
}

Fields

TIMx_CR1: RWRegister<u16>

TIM16/TIM17 control register 1

TIMx_CR2: RWRegister<u16>

TIM16/TIM17 control register 2

TIMx_DIER: RWRegister<u16>

TIM16/TIM17 DMA/interrupt enable register

TIMx_SR: RWRegister<u16>

TIM16/TIM17 status register

TIMx_EGR: WORegister<u32>

event generation register

TIMx_CCER: RWRegister<u16>

TIM16/TIM17 capture/compare enable register

TIMx_CNT: RWRegister<u32>

TIM16/TIM17 counter

TIMx_PSC: RWRegister<u16>

TIM16/TIM17 prescaler

TIMx_ARR: RWRegister<u16>

TIM16/TIM17 auto-reload register

TIMx_RCR: RWRegister<u16>

TIM16/TIM17 repetition counter register

TIMx_CCR1: RWRegister<u16>

TIM16/TIM17 capture/compare register 1

TIMx_BDTR: RWRegister<u32>

As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

TIMx_DCR: RWRegister<u16>

TIM16/TIM17 DMA control register

TIMx_DMAR: RWRegister<u16>

TIM16/TIM17 DMA address for full transfer

TIMx_AF1: RWRegister<u32>

TIM17 alternate function register 1

TIMx_TISEL: RWRegister<u32>

TIM17 input selection register