Struct stm32ral::stm32mp::peripherals::sdmmc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 41 fields
pub SDMMC_POWER: RWRegister<u32>,
pub SDMMC_CLKCR: RWRegister<u32>,
pub SDMMC_ARGR: RWRegister<u32>,
pub SDMMC_CMDR: RWRegister<u32>,
pub SDMMC_RESPCMDR: RORegister<u32>,
pub SDMMC_RESP1R: RORegister<u32>,
pub SDMMC_RESP2R: RORegister<u32>,
pub SDMMC_RESP3R: RORegister<u32>,
pub SDMMC_RESP4R: RORegister<u32>,
pub SDMMC_DTIMER: RWRegister<u32>,
pub SDMMC_DLENR: RWRegister<u32>,
pub SDMMC_DCTRL: RWRegister<u32>,
pub SDMMC_DCNTR: RORegister<u32>,
pub SDMMC_STAR: RORegister<u32>,
pub SDMMC_ICR: RWRegister<u32>,
pub SDMMC_MASKR: RWRegister<u32>,
pub SDMMC_ACKTIMER: RWRegister<u32>,
pub SDMMC_IDMACTRLR: RWRegister<u32>,
pub SDMMC_IDMABSIZER: RWRegister<u32>,
pub SDMMC_IDMABASER: RWRegister<u32>,
pub SDMMC_IDMALAR: RWRegister<u32>,
pub SDMMC_IDMABAR: RWRegister<u32>,
pub SDMMC_FIFOR0: RWRegister<u32>,
pub SDMMC_FIFOR1: RWRegister<u32>,
pub SDMMC_FIFOR2: RWRegister<u32>,
pub SDMMC_FIFOR3: RWRegister<u32>,
pub SDMMC_FIFOR4: RWRegister<u32>,
pub SDMMC_FIFOR5: RWRegister<u32>,
pub SDMMC_FIFOR6: RWRegister<u32>,
pub SDMMC_FIFOR7: RWRegister<u32>,
pub SDMMC_FIFOR8: RWRegister<u32>,
pub SDMMC_FIFOR9: RWRegister<u32>,
pub SDMMC_FIFOR10: RWRegister<u32>,
pub SDMMC_FIFOR11: RWRegister<u32>,
pub SDMMC_FIFOR12: RWRegister<u32>,
pub SDMMC_FIFOR13: RWRegister<u32>,
pub SDMMC_FIFOR14: RWRegister<u32>,
pub SDMMC_FIFOR15: RWRegister<u32>,
pub SDMMC_VERR: RORegister<u32>,
pub SDMMC_IPIDR: RORegister<u32>,
pub SDMMC_SIDR: RORegister<u32>,
// some fields omitted
}Fields
SDMMC_POWER: RWRegister<u32>SDMMC power control register
SDMMC_CLKCR: RWRegister<u32>The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width.
SDMMC_ARGR: RWRegister<u32>The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.
SDMMC_CMDR: RWRegister<u32>The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
SDMMC_RESPCMDR: RORegister<u32>The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).
SDMMC_RESP1R: RORegister<u32>The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
SDMMC_RESP2R: RORegister<u32>The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
SDMMC_RESP3R: RORegister<u32>The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
SDMMC_RESP4R: RORegister<u32>The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.
SDMMC_DTIMER: RWRegister<u32>The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
SDMMC_DLENR: RWRegister<u32>The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
SDMMC_DCTRL: RWRegister<u32>The SDMMC_DCTRL register control the data path state machine (DPSM).
SDMMC_DCNTR: RORegister<u32>The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.
SDMMC_STAR: RORegister<u32>The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)
SDMMC_ICR: RWRegister<u32>The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.
SDMMC_MASKR: RWRegister<u32>The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
SDMMC_ACKTIMER: RWRegister<u32>The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.
SDMMC_IDMACTRLR: RWRegister<u32>The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
SDMMC_IDMABSIZER: RWRegister<u32>The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration.
SDMMC_IDMABASER: RWRegister<u32>The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration.
SDMMC_IDMALAR: RWRegister<u32>SDMMC IDMA linked list address register
SDMMC_IDMABAR: RWRegister<u32>SDMMC IDMA linked list memory base register
SDMMC_FIFOR0: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR1: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR2: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR3: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR4: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR5: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR6: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR7: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR8: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR9: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR10: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR11: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR12: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR13: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR14: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_FIFOR15: RWRegister<u32>The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
SDMMC_VERR: RORegister<u32>SDMMC version register
SDMMC_IPIDR: RORegister<u32>SDMMC identification register
SDMMC_SIDR: RORegister<u32>SDMMC size ID register