Struct stm32ral::stm32mp::peripherals::rcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 224 fields
pub RCC_TZCR: RWRegister<u32>,
pub RCC_OCENSETR: RWRegister<u32>,
pub RCC_OCENCLRR: RWRegister<u32>,
pub RCC_HSICFGR: RWRegister<u32>,
pub RCC_CSICFGR: RWRegister<u32>,
pub RCC_MPCKSELR: RWRegister<u32>,
pub RCC_ASSCKSELR: RWRegister<u32>,
pub RCC_RCK12SELR: RWRegister<u32>,
pub RCC_MPCKDIVR: RWRegister<u32>,
pub RCC_AXIDIVR: RWRegister<u32>,
pub RCC_APB4DIVR: RWRegister<u32>,
pub RCC_APB5DIVR: RWRegister<u32>,
pub RCC_RTCDIVR: RWRegister<u32>,
pub RCC_MSSCKSELR: RWRegister<u32>,
pub RCC_PLL1CR: RWRegister<u32>,
pub RCC_PLL1CFGR1: RWRegister<u32>,
pub RCC_PLL1CFGR2: RWRegister<u32>,
pub RCC_PLL1FRACR: RWRegister<u32>,
pub RCC_PLL1CSGR: RWRegister<u32>,
pub RCC_PLL2CR: RWRegister<u32>,
pub RCC_PLL2CFGR1: RWRegister<u32>,
pub RCC_PLL2CFGR2: RWRegister<u32>,
pub RCC_PLL2FRACR: RWRegister<u32>,
pub RCC_PLL2CSGR: RWRegister<u32>,
pub RCC_I2C46CKSELR: RWRegister<u32>,
pub RCC_SPI6CKSELR: RWRegister<u32>,
pub RCC_UART1CKSELR: RWRegister<u32>,
pub RCC_RNG1CKSELR: RWRegister<u32>,
pub RCC_CPERCKSELR: RWRegister<u32>,
pub RCC_STGENCKSELR: RWRegister<u32>,
pub RCC_DDRITFCR: RWRegister<u32>,
pub RCC_MP_BOOTCR: RWRegister<u32>,
pub RCC_MP_SREQSETR: RWRegister<u32>,
pub RCC_MP_SREQCLRR: RWRegister<u32>,
pub RCC_MP_GCR: RWRegister<u32>,
pub RCC_MP_APRSTCR: RWRegister<u32>,
pub RCC_MP_APRSTSR: RORegister<u32>,
pub RCC_BDCR: RWRegister<u32>,
pub RCC_RDLSICR: RWRegister<u32>,
pub RCC_APB4RSTSETR: RWRegister<u32>,
pub RCC_APB4RSTCLRR: RWRegister<u32>,
pub RCC_APB5RSTSETR: RWRegister<u32>,
pub RCC_APB5RSTCLRR: RWRegister<u32>,
pub RCC_AHB5RSTSETR: RWRegister<u32>,
pub RCC_AHB5RSTCLRR: RWRegister<u32>,
pub RCC_AHB6RSTSETR: RWRegister<u32>,
pub RCC_AHB6RSTCLRR: RWRegister<u32>,
pub RCC_TZAHB6RSTSETR: RWRegister<u32>,
pub RCC_TZAHB6RSTCLRR: RWRegister<u32>,
pub RCC_MP_APB4ENSETR: RWRegister<u32>,
pub RCC_MP_APB4ENCLRR: RWRegister<u32>,
pub RCC_MP_APB5ENSETR: RWRegister<u32>,
pub RCC_MP_APB5ENCLRR: RWRegister<u32>,
pub RCC_MP_AHB5ENSETR: RWRegister<u32>,
pub RCC_MP_AHB5ENCLRR: RWRegister<u32>,
pub RCC_MP_AHB6ENSETR: RWRegister<u32>,
pub RCC_MP_AHB6ENCLRR: RWRegister<u32>,
pub RCC_MP_TZAHB6ENSETR: RWRegister<u32>,
pub RCC_MP_TZAHB6ENCLRR: RWRegister<u32>,
pub RCC_MC_APB4ENSETR: RWRegister<u32>,
pub RCC_MC_APB4ENCLRR: RWRegister<u32>,
pub RCC_MC_APB5ENSETR: RWRegister<u32>,
pub RCC_MC_APB5ENCLRR: RWRegister<u32>,
pub RCC_MC_AHB5ENSETR: RWRegister<u32>,
pub RCC_MC_AHB5ENCLRR: RWRegister<u32>,
pub RCC_MC_AHB6ENSETR: RWRegister<u32>,
pub RCC_MC_AHB6ENCLRR: RWRegister<u32>,
pub RCC_MP_APB4LPENSETR: RWRegister<u32>,
pub RCC_MP_APB4LPENCLRR: RWRegister<u32>,
pub RCC_MP_APB5LPENSETR: RWRegister<u32>,
pub RCC_MP_APB5LPENCLRR: RWRegister<u32>,
pub RCC_MP_AHB5LPENSETR: RWRegister<u32>,
pub RCC_MP_AHB5LPENCLRR: RWRegister<u32>,
pub RCC_MP_AHB6LPENSETR: RWRegister<u32>,
pub RCC_MP_AHB6LPENCLRR: RWRegister<u32>,
pub RCC_MP_TZAHB6LPENSETR: RWRegister<u32>,
pub RCC_MP_TZAHB6LPENCLRR: RWRegister<u32>,
pub RCC_MC_APB4LPENSETR: RWRegister<u32>,
pub RCC_MC_APB4LPENCLRR: RWRegister<u32>,
pub RCC_MC_APB5LPENSETR: RWRegister<u32>,
pub RCC_MC_APB5LPENCLRR: RWRegister<u32>,
pub RCC_MC_AHB5LPENSETR: RWRegister<u32>,
pub RCC_MC_AHB5LPENCLRR: RWRegister<u32>,
pub RCC_MC_AHB6LPENSETR: RWRegister<u32>,
pub RCC_MC_AHB6LPENCLRR: RWRegister<u32>,
pub RCC_BR_RSTSCLRR: RWRegister<u32>,
pub RCC_MP_GRSTCSETR: RWRegister<u32>,
pub RCC_MP_RSTSCLRR: RWRegister<u32>,
pub RCC_MP_IWDGFZSETR: RWRegister<u32>,
pub RCC_MP_IWDGFZCLRR: RWRegister<u32>,
pub RCC_MP_CIER: RWRegister<u32>,
pub RCC_MP_CIFR: RWRegister<u32>,
pub RCC_PWRLPDLYCR: RWRegister<u32>,
pub RCC_MP_RSTSSETR: RWRegister<u32>,
pub RCC_MCO1CFGR: RWRegister<u32>,
pub RCC_MCO2CFGR: RWRegister<u32>,
pub RCC_OCRDYR: RORegister<u32>,
pub RCC_DBGCFGR: RWRegister<u32>,
pub RCC_RCK3SELR: RWRegister<u32>,
pub RCC_RCK4SELR: RWRegister<u32>,
pub RCC_TIMG1PRER: RWRegister<u32>,
pub RCC_TIMG2PRER: RWRegister<u32>,
pub RCC_MCUDIVR: RWRegister<u32>,
pub RCC_APB1DIVR: RWRegister<u32>,
pub RCC_APB2DIVR: RWRegister<u32>,
pub RCC_APB3DIVR: RWRegister<u32>,
pub RCC_PLL3CR: RWRegister<u32>,
pub RCC_PLL3CFGR1: RWRegister<u32>,
pub RCC_PLL3CFGR2: RWRegister<u32>,
pub RCC_PLL3FRACR: RWRegister<u32>,
pub RCC_PLL3CSGR: RWRegister<u32>,
pub RCC_PLL4CR: RWRegister<u32>,
pub RCC_PLL4CFGR1: RWRegister<u32>,
pub RCC_PLL4CFGR2: RWRegister<u32>,
pub RCC_PLL4FRACR: RWRegister<u32>,
pub RCC_PLL4CSGR: RWRegister<u32>,
pub RCC_I2C12CKSELR: RWRegister<u32>,
pub RCC_I2C35CKSELR: RWRegister<u32>,
pub RCC_SAI1CKSELR: RWRegister<u32>,
pub RCC_SAI2CKSELR: RWRegister<u32>,
pub RCC_SAI3CKSELR: RWRegister<u32>,
pub RCC_SAI4CKSELR: RWRegister<u32>,
pub RCC_SPI2S1CKSELR: RWRegister<u32>,
pub RCC_SPI2S23CKSELR: RWRegister<u32>,
pub RCC_SPI45CKSELR: RWRegister<u32>,
pub RCC_UART6CKSELR: RWRegister<u32>,
pub RCC_UART24CKSELR: RWRegister<u32>,
pub RCC_UART35CKSELR: RWRegister<u32>,
pub RCC_UART78CKSELR: RWRegister<u32>,
pub RCC_SDMMC12CKSELR: RWRegister<u32>,
pub RCC_SDMMC3CKSELR: RWRegister<u32>,
pub RCC_ETHCKSELR: RWRegister<u32>,
pub RCC_QSPICKSELR: RWRegister<u32>,
pub RCC_FMCCKSELR: RWRegister<u32>,
pub RCC_FDCANCKSELR: RWRegister<u32>,
pub RCC_SPDIFCKSELR: RWRegister<u32>,
pub RCC_CECCKSELR: RWRegister<u32>,
pub RCC_USBCKSELR: RWRegister<u32>,
pub RCC_RNG2CKSELR: RWRegister<u32>,
pub RCC_DSICKSELR: RWRegister<u32>,
pub RCC_ADCCKSELR: RWRegister<u32>,
pub RCC_LPTIM45CKSELR: RWRegister<u32>,
pub RCC_LPTIM23CKSELR: RWRegister<u32>,
pub RCC_LPTIM1CKSELR: RWRegister<u32>,
pub RCC_APB1RSTSETR: RWRegister<u32>,
pub RCC_APB1RSTCLRR: RWRegister<u32>,
pub RCC_APB2RSTSETR: RWRegister<u32>,
pub RCC_APB2RSTCLRR: RWRegister<u32>,
pub RCC_APB3RSTSETR: RWRegister<u32>,
pub RCC_APB3RSTCLRR: RWRegister<u32>,
pub RCC_AHB2RSTSETR: RWRegister<u32>,
pub RCC_AHB2RSTCLRR: RWRegister<u32>,
pub RCC_AHB3RSTSETR: RWRegister<u32>,
pub RCC_AHB3RSTCLRR: RWRegister<u32>,
pub RCC_AHB4RSTSETR: RWRegister<u32>,
pub RCC_AHB4RSTCLRR: RWRegister<u32>,
pub RCC_MP_APB1ENSETR: RWRegister<u32>,
pub RCC_MP_APB1ENCLRR: RWRegister<u32>,
pub RCC_MP_APB2ENSETR: RWRegister<u32>,
pub RCC_MP_APB2ENCLRR: RWRegister<u32>,
pub RCC_MP_APB3ENSETR: RWRegister<u32>,
pub RCC_MP_APB3ENCLRR: RWRegister<u32>,
pub RCC_MP_AHB2ENSETR: RWRegister<u32>,
pub RCC_MP_AHB2ENCLRR: RWRegister<u32>,
pub RCC_MP_AHB3ENSETR: RWRegister<u32>,
pub RCC_MP_AHB3ENCLRR: RWRegister<u32>,
pub RCC_MP_AHB4ENSETR: RWRegister<u32>,
pub RCC_MP_AHB4ENCLRR: RWRegister<u32>,
pub RCC_MP_MLAHBENSETR: RWRegister<u32>,
pub RCC_MP_MLAHBENCLRR: RWRegister<u32>,
pub RCC_MC_APB1ENSETR: RWRegister<u32>,
pub RCC_MC_APB1ENCLRR: RWRegister<u32>,
pub RCC_MC_APB2ENSETR: RWRegister<u32>,
pub RCC_MC_APB2ENCLRR: RWRegister<u32>,
pub RCC_MC_APB3ENSETR: RWRegister<u32>,
pub RCC_MC_APB3ENCLRR: RWRegister<u32>,
pub RCC_MC_AHB2ENSETR: RWRegister<u32>,
pub RCC_MC_AHB2ENCLRR: RWRegister<u32>,
pub RCC_MC_AHB3ENSETR: RWRegister<u32>,
pub RCC_MC_AHB3ENCLRR: RWRegister<u32>,
pub RCC_MC_AHB4ENSETR: RWRegister<u32>,
pub RCC_MC_AHB4ENCLRR: RWRegister<u32>,
pub RCC_MC_AXIMENSETR: RWRegister<u32>,
pub RCC_MC_AXIMENCLRR: RWRegister<u32>,
pub RCC_MC_MLAHBENSETR: RWRegister<u32>,
pub RCC_MC_MLAHBENCLRR: RWRegister<u32>,
pub RCC_MP_APB1LPENSETR: RWRegister<u32>,
pub RCC_MP_APB1LPENCLRR: RWRegister<u32>,
pub RCC_MP_APB2LPENSETR: RWRegister<u32>,
pub RCC_MP_APB2LPENCLRR: RWRegister<u32>,
pub RCC_MP_APB3LPENSETR: RWRegister<u32>,
pub RCC_MP_APB3LPENCLRR: RWRegister<u32>,
pub RCC_MP_AHB2LPENSETR: RWRegister<u32>,
pub RCC_MP_AHB2LPENCLRR: RWRegister<u32>,
pub RCC_MP_AHB3LPENSETR: RWRegister<u32>,
pub RCC_MP_AHB3LPENCLRR: RWRegister<u32>,
pub RCC_MP_AHB4LPENSETR: RWRegister<u32>,
pub RCC_MP_AHB4LPENCLRR: RWRegister<u32>,
pub RCC_MP_AXIMLPENSETR: RWRegister<u32>,
pub RCC_MP_AXIMLPENCLRR: RWRegister<u32>,
pub RCC_MP_MLAHBLPENSETR: RWRegister<u32>,
pub RCC_MP_MLAHBLPENCLRR: RWRegister<u32>,
pub RCC_MC_APB1LPENSETR: RWRegister<u32>,
pub RCC_MC_APB1LPENCLRR: RWRegister<u32>,
pub RCC_MC_APB2LPENSETR: RWRegister<u32>,
pub RCC_MC_APB2LPENCLRR: RWRegister<u32>,
pub RCC_MC_APB3LPENSETR: RWRegister<u32>,
pub RCC_MC_APB3LPENCLRR: RWRegister<u32>,
pub RCC_MC_AHB2LPENSETR: RWRegister<u32>,
pub RCC_MC_AHB2LPENCLRR: RWRegister<u32>,
pub RCC_MC_AHB3LPENSETR: RWRegister<u32>,
pub RCC_MC_AHB3LPENCLRR: RWRegister<u32>,
pub RCC_MC_AHB4LPENSETR: RWRegister<u32>,
pub RCC_MC_AHB4LPENCLRR: RWRegister<u32>,
pub RCC_MC_AXIMLPENSETR: RWRegister<u32>,
pub RCC_MC_AXIMLPENCLRR: RWRegister<u32>,
pub RCC_MC_MLAHBLPENSETR: RWRegister<u32>,
pub RCC_MC_MLAHBLPENCLRR: RWRegister<u32>,
pub RCC_MC_RSTSCLRR: RWRegister<u32>,
pub RCC_MC_CIER: RWRegister<u32>,
pub RCC_MC_CIFR: RWRegister<u32>,
pub RCC_VERR: RORegister<u32>,
pub RCC_IDR: RORegister<u32>,
pub RCC_SIDR: RORegister<u32>,
// some fields omitted
}Fields
RCC_TZCR: RWRegister<u32>This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.
RCC_OCENSETR: RWRegister<u32>This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_OCENCLRR: RWRegister<u32>This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_HSICFGR: RWRegister<u32>This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_CSICFGR: RWRegister<u32>This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.
RCC_MPCKSELR: RWRegister<u32>This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_ASSCKSELR: RWRegister<u32>This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_RCK12SELR: RWRegister<u32>This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_MPCKDIVR: RWRegister<u32>This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
RCC_AXIDIVR: RWRegister<u32>This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
RCC_APB4DIVR: RWRegister<u32>This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
RCC_APB5DIVR: RWRegister<u32>This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
RCC_RTCDIVR: RWRegister<u32>This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.
RCC_MSSCKSELR: RWRegister<u32>This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL1CR: RWRegister<u32>This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL1CFGR1: RWRegister<u32>This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL1CFGR2: RWRegister<u32>This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL1FRACR: RWRegister<u32>This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL1CSGR: RWRegister<u32>This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL2CR: RWRegister<u32>This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL2CFGR1: RWRegister<u32>This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL2CFGR2: RWRegister<u32>This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL2FRACR: RWRegister<u32>This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_PLL2CSGR: RWRegister<u32>This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.
RCC_I2C46CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
RCC_SPI6CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
RCC_UART1CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
RCC_RNG1CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
RCC_CPERCKSELR: RWRegister<u32>This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.
RCC_STGENCKSELR: RWRegister<u32>This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.
RCC_DDRITFCR: RWRegister<u32>This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.
RCC_MP_BOOTCR: RWRegister<u32>This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.
RCC_MP_SREQSETR: RWRegister<u32>Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
RCC_MP_SREQCLRR: RWRegister<u32>Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.
RCC_MP_GCR: RWRegister<u32>The register contains global control bits. If TZEN = , this register can only be modified in secure mode.
RCC_MP_APRSTCR: RWRegister<u32>This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.
RCC_MP_APRSTSR: RORegister<u32>This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.
RCC_BDCR: RWRegister<u32>This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.
RCC_RDLSICR: RWRegister<u32>This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.
RCC_APB4RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
RCC_APB4RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
RCC_APB5RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_APB5RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_AHB5RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_AHB5RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_AHB6RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.
RCC_AHB6RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.
RCC_TZAHB6RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_TZAHB6RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.
RCC_MP_APB4ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_APB4ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_APB5ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_APB5ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_AHB5ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MP_AHB5ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MP_AHB6ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_AHB6ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .
RCC_MP_TZAHB6ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MP_TZAHB6ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MC_APB4ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_APB4ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_APB5ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_APB5ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_AHB5ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
RCC_MC_AHB5ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.
RCC_MC_AHB6ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_AHB6ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MP_APB4LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_APB4LPENCLRR: RWRegister<u32>This register is used by the MCU
RCC_MP_APB5LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
RCC_MP_APB5LPENCLRR: RWRegister<u32>This register is used by the Mpu.
RCC_MP_AHB5LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
RCC_MP_AHB5LPENCLRR: RWRegister<u32>This register is used by the MCU
RCC_MP_AHB6LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_AHB6LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_TZAHB6LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
RCC_MP_TZAHB6LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.
RCC_MC_APB4LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_APB4LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_APB5LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_APB5LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_AHB5LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.
RCC_MC_AHB5LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.
RCC_MC_AHB6LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_AHB6LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_BR_RSTSCLRR: RWRegister<u32>This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.
RCC_MP_GRSTCSETR: RWRegister<u32>This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.
RCC_MP_RSTSCLRR: RWRegister<u32>This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
RCC_MP_IWDGFZSETR: RWRegister<u32>This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MP_IWDGFZCLRR: RWRegister<u32>This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.
RCC_MP_CIER: RWRegister<u32>This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
RCC_MP_CIFR: RWRegister<u32>This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.
RCC_PWRLPDLYCR: RWRegister<u32>This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.
RCC_MP_RSTSSETR: RWRegister<u32>This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.
RCC_MCO1CFGR: RWRegister<u32>This register is used to select the clock generated on MCO1 output.
RCC_MCO2CFGR: RWRegister<u32>This register is used to select the clock generated on MCO2 output.
RCC_OCRDYR: RORegister<u32>This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.
RCC_DBGCFGR: RWRegister<u32>This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.
RCC_RCK3SELR: RWRegister<u32>This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_RCK4SELR: RWRegister<u32>This register is used to select the reference clock for PLL4.
RCC_TIMG1PRER: RWRegister<u32>This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.
RCC_TIMG2PRER: RWRegister<u32>This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.
RCC_MCUDIVR: RWRegister<u32>This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.
RCC_APB1DIVR: RWRegister<u32>This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.
RCC_APB2DIVR: RWRegister<u32>This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
RCC_APB3DIVR: RWRegister<u32>This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.
RCC_PLL3CR: RWRegister<u32>This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_PLL3CFGR1: RWRegister<u32>This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_PLL3CFGR2: RWRegister<u32>This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_PLL3FRACR: RWRegister<u32>This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_PLL3CSGR: RWRegister<u32>This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_PLL4CR: RWRegister<u32>This register is used to control the PLL4.
RCC_PLL4CFGR1: RWRegister<u32>This register is used to configure the PLL4.
RCC_PLL4CFGR2: RWRegister<u32>This register is used to configure the PLL4.
RCC_PLL4FRACR: RWRegister<u32>This register is used to fine-tune the frequency of the PLL4 VCO.
RCC_PLL4CSGR: RWRegister<u32>This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.
RCC_I2C12CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_I2C35CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SAI1CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SAI2CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SAI3CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SAI4CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SPI2S1CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SPI2S23CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SPI45CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_UART6CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_UART24CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_UART35CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_UART78CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SDMMC12CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SDMMC3CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_ETHCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_QSPICKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_FMCCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_FDCANCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_SPDIFCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.
RCC_CECCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the CEC-HDMI.
RCC_USBCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG
RCC_RNG2CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the RNG2.
RCC_DSICKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the DSI block.
RCC_ADCCKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the ADC block.
RCC_LPTIM45CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.
RCC_LPTIM23CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.
RCC_LPTIM1CKSELR: RWRegister<u32>This register is used to control the selection of the kernel clock for the LPTIM1 block.
RCC_APB1RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral.
RCC_APB1RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_APB2RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral.
RCC_APB2RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_APB3RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral.
RCC_APB3RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_AHB2RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral.
RCC_AHB2RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_AHB3RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral.
RCC_AHB3RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_AHB4RSTSETR: RWRegister<u32>This register is used to activate the reset of the corresponding peripheral
RCC_AHB4RSTCLRR: RWRegister<u32>This register is used to release the reset of the corresponding peripheral.
RCC_MP_APB1ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MP_APB1ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MP_APB2ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MP_APB2ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
RCC_MP_APB3ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MP_APB3ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
RCC_MP_AHB2ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral
RCC_MP_AHB2ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
RCC_MP_AHB3ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral
RCC_MP_AHB3ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
RCC_MP_AHB4ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.
RCC_MP_AHB4ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MP_MLAHBENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MP_MLAHBENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit.
RCC_MC_APB1ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .
RCC_MC_APB1ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit of the corresponding peripheral.
RCC_MC_APB2ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_APB2ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_APB3ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_APB3ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_AHB2ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_AHB2ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_AHB3ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_AHB3ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_AHB4ENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_AHB4ENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_AXIMENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_AXIMENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MC_MLAHBENSETR: RWRegister<u32>This register is used to set the peripheral clock enable bit
RCC_MC_MLAHBENCLRR: RWRegister<u32>This register is used to clear the peripheral clock enable bit
RCC_MP_APB1LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_APB1LPENCLRR: RWRegister<u32>This register is used by the MPU in order to clear the PERxLPEN bits .
RCC_MP_APB2LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_APB2LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_APB3LPENSETR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_APB3LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_AHB2LPENSETR: RWRegister<u32>This register is used by the MPU in order to set the PERxLPEN bit.
RCC_MP_AHB2LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MP_AHB3LPENSETR: RWRegister<u32>This register is used by the MPU
RCC_MP_AHB3LPENCLRR: RWRegister<u32>This register is used by the MPU in order to clear the PERxLPEN bit
RCC_MP_AHB4LPENSETR: RWRegister<u32>This register is used by the MPU
RCC_MP_AHB4LPENCLRR: RWRegister<u32>This register is used by the MPU
RCC_MP_AXIMLPENSETR: RWRegister<u32>This register is used by the MPU
RCC_MP_AXIMLPENCLRR: RWRegister<u32>This register is used by the MPU
RCC_MP_MLAHBLPENSETR: RWRegister<u32>This register is used by the MPU in order to set the PERxLPEN bit
RCC_MP_MLAHBLPENCLRR: RWRegister<u32>This register is used by the MPU in order to clear the PERxLPEN bit
RCC_MC_APB1LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_APB1LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bits
RCC_MC_APB2LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_APB2LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_APB3LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_APB3LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_AHB2LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_AHB2LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_AHB3LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_AHB3LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit
RCC_MC_AHB4LPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit.
RCC_MC_AHB4LPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
RCC_MC_AXIMLPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
RCC_MC_AXIMLPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
RCC_MC_MLAHBLPENSETR: RWRegister<u32>This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.
RCC_MC_MLAHBLPENCLRR: RWRegister<u32>This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.
RCC_MC_RSTSCLRR: RWRegister<u32>This register is used by the MCU to check the reset source.
RCC_MC_CIER: RWRegister<u32>This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.
RCC_MC_CIFR: RWRegister<u32>This register shall be used by the MCU in order to read and clear the interrupt flags.
RCC_VERR: RORegister<u32>This register gives the IP version
RCC_IDR: RORegister<u32>This register gives the unique identifier of the RCC
RCC_SIDR: RORegister<u32>This register gives the decoding space, which is for the RCC of 4 kB.