Struct stm32ral::stm32mp::peripherals::otg::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 241 fields
pub OTG_GOTGCTL: RWRegister<u32>,
pub OTG_GOTGINT: RWRegister<u32>,
pub OTG_GAHBCFG: RWRegister<u32>,
pub OTG_GUSBCFG: RWRegister<u32>,
pub OTG_GRSTCTL: RWRegister<u32>,
pub OTG_GINTSTS: RWRegister<u32>,
pub OTG_GINTMSK: RWRegister<u32>,
pub OTG_GRXSTSR: RORegister<u32>,
pub OTG_GRXSTSP: RORegister<u32>,
pub OTG_GRXFSIZ: RWRegister<u32>,
pub OTG_HNPTXFSIZ: RWRegister<u32>,
pub OTG_HNPTXSTS: RORegister<u32>,
pub OTG_GCCFG: RWRegister<u32>,
pub OTG_CID: RWRegister<u32>,
pub OTG_GLPMCFG: RWRegister<u32>,
pub OTG_HPTXFSIZ: RWRegister<u32>,
pub OTG_DIEPTXF1: RWRegister<u32>,
pub OTG_DIEPTXF2: RWRegister<u32>,
pub OTG_DIEPTXF3: RWRegister<u32>,
pub OTG_DIEPTXF4: RWRegister<u32>,
pub OTG_DIEPTXF5: RWRegister<u32>,
pub OTG_DIEPTXF6: RWRegister<u32>,
pub OTG_DIEPTXF7: RWRegister<u32>,
pub OTG_DIEPTXF8: RWRegister<u32>,
pub OTG_HCFG: RWRegister<u32>,
pub OTG_HFIR: RWRegister<u32>,
pub OTG_HFNUM: RORegister<u32>,
pub OTG_HPTXSTS: RORegister<u32>,
pub OTG_HAINT: RORegister<u32>,
pub OTG_HAINTMSK: RWRegister<u32>,
pub OTG_HFLBADDR: RWRegister<u32>,
pub OTG_HPRT: RWRegister<u32>,
pub OTG_HCCHAR0: RWRegister<u32>,
pub OTG_HCSPLT0: RWRegister<u32>,
pub OTG_HCINT0: RWRegister<u32>,
pub OTG_HCINTMSK0: RWRegister<u32>,
pub OTG_HCTSIZ0: RWRegister<u32>,
pub OTG_HCDMA0: RWRegister<u32>,
pub OTG_HCDMAB0: RORegister<u32>,
pub OTG_HCCHAR1: RWRegister<u32>,
pub OTG_HCSPLT1: RWRegister<u32>,
pub OTG_HCINT1: RWRegister<u32>,
pub OTG_HCINTMSK1: RWRegister<u32>,
pub OTG_HCTSIZ1: RWRegister<u32>,
pub OTG_HCDMA1: RWRegister<u32>,
pub OTG_HCDMAB1: RORegister<u32>,
pub OTG_HCCHAR2: RWRegister<u32>,
pub OTG_HCSPLT2: RWRegister<u32>,
pub OTG_HCINT2: RWRegister<u32>,
pub OTG_HCINTMSK2: RWRegister<u32>,
pub OTG_HCTSIZ2: RWRegister<u32>,
pub OTG_HCDMA2: RWRegister<u32>,
pub OTG_HCDMAB2: RORegister<u32>,
pub OTG_HCCHAR3: RWRegister<u32>,
pub OTG_HCSPLT3: RWRegister<u32>,
pub OTG_HCINT3: RWRegister<u32>,
pub OTG_HCINTMSK3: RWRegister<u32>,
pub OTG_HCTSIZ3: RWRegister<u32>,
pub OTG_HCDMA3: RWRegister<u32>,
pub OTG_HCDMAB3: RORegister<u32>,
pub OTG_HCCHAR4: RWRegister<u32>,
pub OTG_HCSPLT4: RWRegister<u32>,
pub OTG_HCINT4: RWRegister<u32>,
pub OTG_HCINTMSK4: RWRegister<u32>,
pub OTG_HCTSIZ4: RWRegister<u32>,
pub OTG_HCDMA4: RWRegister<u32>,
pub OTG_HCDMAB4: RORegister<u32>,
pub OTG_HCCHAR5: RWRegister<u32>,
pub OTG_HCSPLT5: RWRegister<u32>,
pub OTG_HCINT5: RWRegister<u32>,
pub OTG_HCINTMSK5: RWRegister<u32>,
pub OTG_HCTSIZ5: RWRegister<u32>,
pub OTG_HCDMA5: RWRegister<u32>,
pub OTG_HCDMAB5: RORegister<u32>,
pub OTG_HCCHAR6: RWRegister<u32>,
pub OTG_HCSPLT6: RWRegister<u32>,
pub OTG_HCINT6: RWRegister<u32>,
pub OTG_HCINTMSK6: RWRegister<u32>,
pub OTG_HCTSIZ6: RWRegister<u32>,
pub OTG_HCDMA6: RWRegister<u32>,
pub OTG_HCDMAB6: RORegister<u32>,
pub OTG_HCCHAR7: RWRegister<u32>,
pub OTG_HCSPLT7: RWRegister<u32>,
pub OTG_HCINT7: RWRegister<u32>,
pub OTG_HCINTMSK7: RWRegister<u32>,
pub OTG_HCTSIZ7: RWRegister<u32>,
pub OTG_HCDMA7: RWRegister<u32>,
pub OTG_HCDMAB7: RORegister<u32>,
pub OTG_HCCHAR8: RWRegister<u32>,
pub OTG_HCSPLT8: RWRegister<u32>,
pub OTG_HCINT8: RWRegister<u32>,
pub OTG_HCINTMSK8: RWRegister<u32>,
pub OTG_HCTSIZ8: RWRegister<u32>,
pub OTG_HCDMA8: RWRegister<u32>,
pub OTG_HCDMAB8: RORegister<u32>,
pub OTG_HCCHAR9: RWRegister<u32>,
pub OTG_HCSPLT9: RWRegister<u32>,
pub OTG_HCINT9: RWRegister<u32>,
pub OTG_HCINTMSK9: RWRegister<u32>,
pub OTG_HCTSIZ9: RWRegister<u32>,
pub OTG_HCDMA9: RWRegister<u32>,
pub OTG_HCDMAB9: RORegister<u32>,
pub OTG_HCCHAR10: RWRegister<u32>,
pub OTG_HCSPLT10: RWRegister<u32>,
pub OTG_HCINT10: RWRegister<u32>,
pub OTG_HCINTMSK10: RWRegister<u32>,
pub OTG_HCTSIZ10: RWRegister<u32>,
pub OTG_HCDMA10: RWRegister<u32>,
pub OTG_HCDMAB10: RORegister<u32>,
pub OTG_HCCHAR11: RWRegister<u32>,
pub OTG_HCSPLT11: RWRegister<u32>,
pub OTG_HCINT11: RWRegister<u32>,
pub OTG_HCINTMSK11: RWRegister<u32>,
pub OTG_HCTSIZ11: RWRegister<u32>,
pub OTG_HCDMA11: RWRegister<u32>,
pub OTG_HCDMAB11: RORegister<u32>,
pub OTG_HCCHAR12: RWRegister<u32>,
pub OTG_HCSPLT12: RWRegister<u32>,
pub OTG_HCINT12: RWRegister<u32>,
pub OTG_HCINTMSK12: RWRegister<u32>,
pub OTG_HCTSIZ12: RWRegister<u32>,
pub OTG_HCDMA12: RWRegister<u32>,
pub OTG_HCDMAB12: RORegister<u32>,
pub OTG_HCCHAR13: RWRegister<u32>,
pub OTG_HCSPLT13: RWRegister<u32>,
pub OTG_HCINT13: RWRegister<u32>,
pub OTG_HCINTMSK13: RWRegister<u32>,
pub OTG_HCTSIZ13: RWRegister<u32>,
pub OTG_HCDMA13: RWRegister<u32>,
pub OTG_HCDMAB13: RORegister<u32>,
pub OTG_HCCHAR14: RWRegister<u32>,
pub OTG_HCSPLT14: RWRegister<u32>,
pub OTG_HCINT14: RWRegister<u32>,
pub OTG_HCINTMSK14: RWRegister<u32>,
pub OTG_HCTSIZ14: RWRegister<u32>,
pub OTG_HCDMA14: RWRegister<u32>,
pub OTG_HCDMAB14: RORegister<u32>,
pub OTG_HCCHAR15: RWRegister<u32>,
pub OTG_HCSPLT15: RWRegister<u32>,
pub OTG_HCINT15: RWRegister<u32>,
pub OTG_HCINTMSK15: RWRegister<u32>,
pub OTG_HCTSIZ15: RWRegister<u32>,
pub OTG_HCDMA15: RWRegister<u32>,
pub OTG_HCDMAB15: RORegister<u32>,
pub OTG_DCFG: RWRegister<u32>,
pub OTG_DCTL: RWRegister<u32>,
pub OTG_DSTS: RORegister<u32>,
pub OTG_DIEPMSK: RWRegister<u32>,
pub OTG_DOEPMSK: RWRegister<u32>,
pub OTG_DAINT: RORegister<u32>,
pub OTG_DAINTMSK: RWRegister<u32>,
pub OTG_DVBUSDIS: RWRegister<u32>,
pub OTG_DVBUSPULSE: RWRegister<u32>,
pub OTG_DTHRCTL: RWRegister<u32>,
pub OTG_DIEPEMPMSK: RWRegister<u32>,
pub OTG_DEACHINT: RORegister<u32>,
pub OTG_DEACHINTMSK: RWRegister<u32>,
pub OTG_HS_DIEPEACHMSK1: RWRegister<u32>,
pub OTG_HS_DOEPEACHMSK1: RWRegister<u32>,
pub OTG_DIEPCTL0: RWRegister<u32>,
pub OTG_DIEPINT0: RWRegister<u32>,
pub OTG_DIEPTSIZ0: RWRegister<u32>,
pub OTG_DIEPDMA0: RWRegister<u32>,
pub OTG_DTXFSTS0: RORegister<u32>,
pub OTG_DIEPCTL1: RWRegister<u32>,
pub OTG_DIEPINT1: RWRegister<u32>,
pub OTG_DIEPTSIZ1: RWRegister<u32>,
pub OTG_DIEPDMA1: RWRegister<u32>,
pub OTG_DTXFSTS1: RORegister<u32>,
pub OTG_DIEPCTL2: RWRegister<u32>,
pub OTG_DIEPINT2: RWRegister<u32>,
pub OTG_DIEPTSIZ2: RWRegister<u32>,
pub OTG_DIEPDMA2: RWRegister<u32>,
pub OTG_DTXFSTS2: RORegister<u32>,
pub OTG_DIEPCTL3: RWRegister<u32>,
pub OTG_DIEPINT3: RWRegister<u32>,
pub OTG_DIEPTSIZ3: RWRegister<u32>,
pub OTG_DIEPDMA3: RWRegister<u32>,
pub OTG_DTXFSTS3: RORegister<u32>,
pub OTG_DIEPCTL4: RWRegister<u32>,
pub OTG_DIEPINT4: RWRegister<u32>,
pub OTG_DIEPTSIZ4: RWRegister<u32>,
pub OTG_DIEPDMA4: RWRegister<u32>,
pub OTG_DTXFSTS4: RORegister<u32>,
pub OTG_DIEPCTL5: RWRegister<u32>,
pub OTG_DIEPINT5: RWRegister<u32>,
pub OTG_DIEPTSIZ5: RWRegister<u32>,
pub OTG_DIEPDMA5: RWRegister<u32>,
pub OTG_DTXFSTS5: RORegister<u32>,
pub OTG_DIEPCTL6: RWRegister<u32>,
pub OTG_DIEPINT6: RWRegister<u32>,
pub OTG_DIEPTSIZ6: RWRegister<u32>,
pub OTG_DIEPDMA6: RWRegister<u32>,
pub OTG_DTXFSTS6: RORegister<u32>,
pub OTG_DIEPCTL7: RWRegister<u32>,
pub OTG_DIEPINT7: RWRegister<u32>,
pub OTG_DIEPTSIZ7: RWRegister<u32>,
pub OTG_DIEPDMA7: RWRegister<u32>,
pub OTG_DTXFSTS7: RORegister<u32>,
pub OTG_DIEPCTL8: RWRegister<u32>,
pub OTG_DIEPINT8: RWRegister<u32>,
pub OTG_DIEPTSIZ8: RWRegister<u32>,
pub OTG_DIEPDMA8: RWRegister<u32>,
pub OTG_DTXFSTS8: RORegister<u32>,
pub OTG_DOEPCTL0: RWRegister<u32>,
pub OTG_DOEPINT0: RWRegister<u32>,
pub OTG_DOEPTSIZ0: RWRegister<u32>,
pub OTG_DOEPDMA0: RWRegister<u32>,
pub OTG_DOEPCTL1: RWRegister<u32>,
pub OTG_DOEPINT1: RWRegister<u32>,
pub OTG_DOEPTSIZ1: RWRegister<u32>,
pub OTG_DOEPDMA1: RWRegister<u32>,
pub OTG_DOEPCTL2: RWRegister<u32>,
pub OTG_DOEPINT2: RWRegister<u32>,
pub OTG_DOEPTSIZ2: RWRegister<u32>,
pub OTG_DOEPDMA2: RWRegister<u32>,
pub OTG_DOEPCTL3: RWRegister<u32>,
pub OTG_DOEPINT3: RWRegister<u32>,
pub OTG_DOEPTSIZ3: RWRegister<u32>,
pub OTG_DOEPDMA3: RWRegister<u32>,
pub OTG_DOEPCTL4: RWRegister<u32>,
pub OTG_DOEPINT4: RWRegister<u32>,
pub OTG_DOEPTSIZ4: RWRegister<u32>,
pub OTG_DOEPDMA4: RWRegister<u32>,
pub OTG_DOEPCTL5: RWRegister<u32>,
pub OTG_DOEPINT5: RWRegister<u32>,
pub OTG_DOEPTSIZ5: RWRegister<u32>,
pub OTG_DOEPDMA5: RWRegister<u32>,
pub OTG_DOEPCTL6: RWRegister<u32>,
pub OTG_DOEPINT6: RWRegister<u32>,
pub OTG_DOEPTSIZ6: RWRegister<u32>,
pub OTG_DOEPDMA6: RWRegister<u32>,
pub OTG_DOEPCTL7: RWRegister<u32>,
pub OTG_DOEPINT7: RWRegister<u32>,
pub OTG_DOEPTSIZ7: RWRegister<u32>,
pub OTG_DOEPDMA7: RWRegister<u32>,
pub OTG_DOEPCTL8: RWRegister<u32>,
pub OTG_DOEPINT8: RWRegister<u32>,
pub OTG_DOEPTSIZ8: RWRegister<u32>,
pub OTG_DOEPDMA8: RWRegister<u32>,
pub OTG_PCGCCTL: RWRegister<u32>,
// some fields omitted
}Fields
OTG_GOTGCTL: RWRegister<u32>The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
OTG_GOTGINT: RWRegister<u32>The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
OTG_GAHBCFG: RWRegister<u32>This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
OTG_GUSBCFG: RWRegister<u32>This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
OTG_GRSTCTL: RWRegister<u32>The application uses this register to reset various hardware features inside the core.
OTG_GINTSTS: RWRegister<u32>This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
OTG_GINTMSK: RWRegister<u32>This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
OTG_GRXSTSR: RORegister<u32>This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
OTG_GRXSTSP: RORegister<u32>This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
OTG_GRXFSIZ: RWRegister<u32>The application can program the RAM size that must be allocated to the Rx FIFO.
OTG_HNPTXFSIZ: RWRegister<u32>Host mode
OTG_HNPTXSTS: RORegister<u32>In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
OTG_GCCFG: RWRegister<u32>OTG general core configuration register
OTG_CID: RWRegister<u32>This is a register containing the Product ID as reset value.
OTG_GLPMCFG: RWRegister<u32>OTG core LPM configuration register
OTG_HPTXFSIZ: RWRegister<u32>OTG host periodic transmit FIFO size register
OTG_DIEPTXF1: RWRegister<u32>OTG device IN endpoint transmit FIFO 1 size register
OTG_DIEPTXF2: RWRegister<u32>OTG device IN endpoint transmit FIFO 2 size register
OTG_DIEPTXF3: RWRegister<u32>OTG device IN endpoint transmit FIFO 3 size register
OTG_DIEPTXF4: RWRegister<u32>OTG device IN endpoint transmit FIFO 4 size register
OTG_DIEPTXF5: RWRegister<u32>OTG device IN endpoint transmit FIFO 5 size register
OTG_DIEPTXF6: RWRegister<u32>OTG device IN endpoint transmit FIFO 6 size register
OTG_DIEPTXF7: RWRegister<u32>OTG device IN endpoint transmit FIFO 7 size register
OTG_DIEPTXF8: RWRegister<u32>OTG device IN endpoint transmit FIFO 8 size register
OTG_HCFG: RWRegister<u32>This register configures the core after power-on. Do not make changes to this register after initializing the host.
OTG_HFIR: RWRegister<u32>This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
OTG_HFNUM: RORegister<u32>This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
OTG_HPTXSTS: RORegister<u32>This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
OTG_HAINT: RORegister<u32>When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
OTG_HAINTMSK: RWRegister<u32>The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
OTG_HFLBADDR: RWRegister<u32>This register holds the starting address of the frame list information (scatter/gather mode).
OTG_HPRT: RWRegister<u32>This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
OTG_HCCHAR0: RWRegister<u32>OTG host channel 0 characteristics register
OTG_HCSPLT0: RWRegister<u32>OTG host channel 0 split control register
OTG_HCINT0: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK0: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ0: RWRegister<u32>OTG host channel 0 transfer size register
OTG_HCDMA0: RWRegister<u32>OTG host channel 0 DMA address register in buffer DMA [alternate]
OTG_HCDMAB0: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR1: RWRegister<u32>OTG host channel 1 characteristics register
OTG_HCSPLT1: RWRegister<u32>OTG host channel 1 split control register
OTG_HCINT1: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK1: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ1: RWRegister<u32>OTG host channel 1 transfer size register
OTG_HCDMA1: RWRegister<u32>OTG host channel 1 DMA address register in buffer DMA [alternate]
OTG_HCDMAB1: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR2: RWRegister<u32>OTG host channel 2 characteristics register
OTG_HCSPLT2: RWRegister<u32>OTG host channel 2 split control register
OTG_HCINT2: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK2: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ2: RWRegister<u32>OTG host channel 2 transfer size register
OTG_HCDMA2: RWRegister<u32>OTG host channel 2 DMA address register in buffer DMA [alternate]
OTG_HCDMAB2: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR3: RWRegister<u32>OTG host channel 3 characteristics register
OTG_HCSPLT3: RWRegister<u32>OTG host channel 3 split control register
OTG_HCINT3: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK3: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ3: RWRegister<u32>OTG host channel 3 transfer size register
OTG_HCDMA3: RWRegister<u32>OTG host channel 3 DMA address register in buffer DMA [alternate]
OTG_HCDMAB3: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR4: RWRegister<u32>OTG host channel 4 characteristics register
OTG_HCSPLT4: RWRegister<u32>OTG host channel 4 split control register
OTG_HCINT4: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK4: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ4: RWRegister<u32>OTG host channel 4 transfer size register
OTG_HCDMA4: RWRegister<u32>OTG host channel 4 DMA address register in buffer DMA [alternate]
OTG_HCDMAB4: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR5: RWRegister<u32>OTG host channel 5 characteristics register
OTG_HCSPLT5: RWRegister<u32>OTG host channel 5 split control register
OTG_HCINT5: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK5: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ5: RWRegister<u32>OTG host channel 5 transfer size register
OTG_HCDMA5: RWRegister<u32>OTG host channel 5 DMA address register in buffer DMA [alternate]
OTG_HCDMAB5: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR6: RWRegister<u32>OTG host channel 6 characteristics register
OTG_HCSPLT6: RWRegister<u32>OTG host channel 6 split control register
OTG_HCINT6: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK6: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ6: RWRegister<u32>OTG host channel 6 transfer size register
OTG_HCDMA6: RWRegister<u32>OTG host channel 6 DMA address register in buffer DMA [alternate]
OTG_HCDMAB6: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR7: RWRegister<u32>OTG host channel 7 characteristics register
OTG_HCSPLT7: RWRegister<u32>OTG host channel 7 split control register
OTG_HCINT7: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK7: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ7: RWRegister<u32>OTG host channel 7 transfer size register
OTG_HCDMA7: RWRegister<u32>OTG host channel 7 DMA address register in buffer DMA [alternate]
OTG_HCDMAB7: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR8: RWRegister<u32>OTG host channel 8 characteristics register
OTG_HCSPLT8: RWRegister<u32>OTG host channel 8 split control register
OTG_HCINT8: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK8: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ8: RWRegister<u32>OTG host channel 8 transfer size register
OTG_HCDMA8: RWRegister<u32>OTG host channel 8 DMA address register in buffer DMA [alternate]
OTG_HCDMAB8: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR9: RWRegister<u32>OTG host channel 9 characteristics register
OTG_HCSPLT9: RWRegister<u32>OTG host channel 9 split control register
OTG_HCINT9: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK9: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ9: RWRegister<u32>OTG host channel 9 transfer size register
OTG_HCDMA9: RWRegister<u32>OTG host channel 9 DMA address register in buffer DMA [alternate]
OTG_HCDMAB9: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR10: RWRegister<u32>OTG host channel 10 characteristics register
OTG_HCSPLT10: RWRegister<u32>OTG host channel 10 split control register
OTG_HCINT10: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK10: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ10: RWRegister<u32>OTG host channel 10 transfer size register
OTG_HCDMA10: RWRegister<u32>OTG host channel 10 DMA address register in buffer DMA [alternate]
OTG_HCDMAB10: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR11: RWRegister<u32>OTG host channel 11 characteristics register
OTG_HCSPLT11: RWRegister<u32>OTG host channel 11 split control register
OTG_HCINT11: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK11: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ11: RWRegister<u32>OTG host channel 11 transfer size register
OTG_HCDMA11: RWRegister<u32>OTG host channel 11 DMA address register in buffer DMA [alternate]
OTG_HCDMAB11: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR12: RWRegister<u32>OTG host channel 12 characteristics register
OTG_HCSPLT12: RWRegister<u32>OTG host channel 12 split control register
OTG_HCINT12: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK12: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ12: RWRegister<u32>OTG host channel 12 transfer size register
OTG_HCDMA12: RWRegister<u32>OTG host channel 12 DMA address register in buffer DMA [alternate]
OTG_HCDMAB12: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR13: RWRegister<u32>OTG host channel 13 characteristics register
OTG_HCSPLT13: RWRegister<u32>OTG host channel 13 split control register
OTG_HCINT13: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK13: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ13: RWRegister<u32>OTG host channel 13 transfer size register
OTG_HCDMA13: RWRegister<u32>OTG host channel 13 DMA address register in buffer DMA [alternate]
OTG_HCDMAB13: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR14: RWRegister<u32>OTG host channel 14 characteristics register
OTG_HCSPLT14: RWRegister<u32>OTG host channel 14 split control register
OTG_HCINT14: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK14: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ14: RWRegister<u32>OTG host channel 14 transfer size register
OTG_HCDMA14: RWRegister<u32>OTG host channel 14 DMA address register in buffer DMA [alternate]
OTG_HCDMAB14: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_HCCHAR15: RWRegister<u32>OTG host channel 15 characteristics register
OTG_HCSPLT15: RWRegister<u32>OTG host channel 15 split control register
OTG_HCINT15: RWRegister<u32>This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
OTG_HCINTMSK15: RWRegister<u32>This register reflects the mask for each channel status described in the previous section.
OTG_HCTSIZ15: RWRegister<u32>OTG host channel 15 transfer size register
OTG_HCDMA15: RWRegister<u32>OTG host channel 15 DMA address register in buffer DMA [alternate]
OTG_HCDMAB15: RORegister<u32>OTG host channel-n DMA address buffer register
OTG_DCFG: RWRegister<u32>This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
OTG_DCTL: RWRegister<u32>OTG device control register
OTG_DSTS: RORegister<u32>This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
OTG_DIEPMSK: RWRegister<u32>This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
OTG_DOEPMSK: RWRegister<u32>This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
OTG_DAINT: RORegister<u32>When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
OTG_DAINTMSK: RWRegister<u32>The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
OTG_DVBUSDIS: RWRegister<u32>This register specifies the VBUS discharge time after VBUS pulsing during SRP.
OTG_DVBUSPULSE: RWRegister<u32>This register specifies the VBUS pulsing time during SRP.
OTG_DTHRCTL: RWRegister<u32>OTG device threshold control register
OTG_DIEPEMPMSK: RWRegister<u32>This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
OTG_DEACHINT: RORegister<u32>OTG device each endpoint interrupt register
OTG_DEACHINTMSK: RWRegister<u32>There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
OTG_HS_DIEPEACHMSK1: RWRegister<u32>This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
OTG_HS_DOEPEACHMSK1: RWRegister<u32>This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
OTG_DIEPCTL0: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT0: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ0: RWRegister<u32>The application must modify this register before enabling endpoint 0.
OTG_DIEPDMA0: RWRegister<u32>OTG device IN endpoint 0 DMA address register
OTG_DTXFSTS0: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL1: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT1: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ1: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA1: RWRegister<u32>OTG device IN endpoint 1 DMA address register
OTG_DTXFSTS1: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL2: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT2: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ2: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA2: RWRegister<u32>OTG device IN endpoint 2 DMA address register
OTG_DTXFSTS2: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL3: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT3: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ3: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA3: RWRegister<u32>OTG device IN endpoint 3 DMA address register
OTG_DTXFSTS3: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL4: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT4: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ4: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA4: RWRegister<u32>OTG device IN endpoint 4 DMA address register
OTG_DTXFSTS4: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL5: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT5: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ5: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA5: RWRegister<u32>OTG device IN endpoint 5 DMA address register
OTG_DTXFSTS5: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL6: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT6: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ6: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA6: RWRegister<u32>OTG device IN endpoint 6 DMA address register
OTG_DTXFSTS6: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL7: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT7: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ7: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA7: RWRegister<u32>OTG device IN endpoint 7 DMA address register
OTG_DTXFSTS7: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DIEPCTL8: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DIEPINT8: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DIEPTSIZ8: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DIEPDMA8: RWRegister<u32>OTG device IN endpoint 8 DMA address register
OTG_DTXFSTS8: RORegister<u32>This read-only register contains the free space information for the device IN endpoint Tx FIFO.
OTG_DOEPCTL0: RWRegister<u32>This section describes the OTG_DOEPCTL0 register.
OTG_DOEPINT0: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ0: RWRegister<u32>The application must modify this register before enabling endpoint 0.
OTG_DOEPDMA0: RWRegister<u32>OTG device OUT endpoint 0 DMA address register
OTG_DOEPCTL1: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT1: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ1: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA1: RWRegister<u32>OTG device OUT endpoint 1 DMA address register
OTG_DOEPCTL2: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT2: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ2: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA2: RWRegister<u32>OTG device OUT endpoint 2 DMA address register
OTG_DOEPCTL3: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT3: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ3: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA3: RWRegister<u32>OTG device OUT endpoint 3 DMA address register
OTG_DOEPCTL4: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT4: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ4: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA4: RWRegister<u32>OTG device OUT endpoint 4 DMA address register
OTG_DOEPCTL5: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT5: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ5: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA5: RWRegister<u32>OTG device OUT endpoint 5 DMA address register
OTG_DOEPCTL6: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT6: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ6: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA6: RWRegister<u32>OTG device OUT endpoint 6 DMA address register
OTG_DOEPCTL7: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT7: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ7: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA7: RWRegister<u32>OTG device OUT endpoint 7 DMA address register
OTG_DOEPCTL8: RWRegister<u32>The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
OTG_DOEPINT8: RWRegister<u32>This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
OTG_DOEPTSIZ8: RWRegister<u32>The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
OTG_DOEPDMA8: RWRegister<u32>OTG device OUT endpoint 8 DMA address register
OTG_PCGCCTL: RWRegister<u32>This register is available in host and device modes.