Struct stm32ral::stm32mp::peripherals::gpiog::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub GPIOG_MODER: RWRegister<u32>,
    pub GPIOG_OTYPER: RWRegister<u32>,
    pub GPIOG_OSPEEDR: RWRegister<u32>,
    pub GPIOG_PUPDR: RWRegister<u32>,
    pub GPIOG_IDR: RORegister<u32>,
    pub GPIOG_ODR: RWRegister<u32>,
    pub GPIOG_BSRR: WORegister<u32>,
    pub GPIOG_LCKR: RWRegister<u32>,
    pub GPIOG_AFRL: RWRegister<u32>,
    pub GPIOG_AFRH: RWRegister<u32>,
    pub GPIOG_BRR: WORegister<u32>,
    pub GPIOG_HWCFGR10: RORegister<u32>,
    pub GPIOG_HWCFGR9: RORegister<u32>,
    pub GPIOG_HWCFGR8: RORegister<u32>,
    pub GPIOG_HWCFGR7: RORegister<u32>,
    pub GPIOG_HWCFGR6: RORegister<u32>,
    pub GPIOG_HWCFGR5: RORegister<u32>,
    pub GPIOG_HWCFGR4: RORegister<u32>,
    pub GPIOG_HWCFGR3: RORegister<u32>,
    pub GPIOG_HWCFGR2: RORegister<u32>,
    pub GPIOG_HWCFGR1: RORegister<u32>,
    pub GPIOG_HWCFGR0: RORegister<u32>,
    pub GPIOG_VERR: RORegister<u32>,
    pub GPIOG_IPIDR: RORegister<u32>,
    pub GPIOG_SIDR: RORegister<u32>,
    // some fields omitted
}

Fields

GPIOG_MODER: RWRegister<u32>

GPIO port mode register

GPIOG_OTYPER: RWRegister<u32>

GPIO port output type register

GPIOG_OSPEEDR: RWRegister<u32>

GPIO port output speed register

GPIOG_PUPDR: RWRegister<u32>

GPIO port pull-up/pull-down register

GPIOG_IDR: RORegister<u32>

GPIO port input data register

GPIOG_ODR: RWRegister<u32>

GPIO port output data register

GPIOG_BSRR: WORegister<u32>

GPIO port bit set/reset register

GPIOG_LCKR: RWRegister<u32>

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

GPIOG_AFRL: RWRegister<u32>

GPIO alternate function low register

GPIOG_AFRH: RWRegister<u32>

GPIO alternate function high register

GPIOG_BRR: WORegister<u32>

GPIO port bit reset register

GPIOG_HWCFGR10: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

GPIOG_HWCFGR9: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOG_HWCFGR8: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOG_HWCFGR7: RORegister<u32>

GPIO hardware configuration register 7

GPIOG_HWCFGR6: RORegister<u32>

GPIO hardware configuration register 6

GPIOG_HWCFGR5: RORegister<u32>

GPIO hardware configuration register 5

GPIOG_HWCFGR4: RORegister<u32>

GPIO hardware configuration register 4

GPIOG_HWCFGR3: RORegister<u32>

GPIO hardware configuration register 3

GPIOG_HWCFGR2: RORegister<u32>

GPIO hardware configuration register 2

GPIOG_HWCFGR1: RORegister<u32>

GPIO hardware configuration register 1

GPIOG_HWCFGR0: RORegister<u32>

GPIO hardware configuration register 0

GPIOG_VERR: RORegister<u32>

GPIO version register

GPIOG_IPIDR: RORegister<u32>

GPIO identification register

GPIOG_SIDR: RORegister<u32>

GPIO size identification register