Struct stm32ral::stm32mp::peripherals::gpioc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub GPIOC_MODER: RWRegister<u32>,
    pub GPIOC_OTYPER: RWRegister<u32>,
    pub GPIOC_OSPEEDR: RWRegister<u32>,
    pub GPIOC_PUPDR: RWRegister<u32>,
    pub GPIOC_IDR: RORegister<u32>,
    pub GPIOC_ODR: RWRegister<u32>,
    pub GPIOC_BSRR: WORegister<u32>,
    pub GPIOC_LCKR: RWRegister<u32>,
    pub GPIOC_AFRL: RWRegister<u32>,
    pub GPIOC_AFRH: RWRegister<u32>,
    pub GPIOC_BRR: WORegister<u32>,
    pub GPIOC_HWCFGR10: RORegister<u32>,
    pub GPIOC_HWCFGR9: RORegister<u32>,
    pub GPIOC_HWCFGR8: RORegister<u32>,
    pub GPIOC_HWCFGR7: RORegister<u32>,
    pub GPIOC_HWCFGR6: RORegister<u32>,
    pub GPIOC_HWCFGR5: RORegister<u32>,
    pub GPIOC_HWCFGR4: RORegister<u32>,
    pub GPIOC_HWCFGR3: RORegister<u32>,
    pub GPIOC_HWCFGR2: RORegister<u32>,
    pub GPIOC_HWCFGR1: RORegister<u32>,
    pub GPIOC_HWCFGR0: RORegister<u32>,
    pub GPIOC_VERR: RORegister<u32>,
    pub GPIOC_IPIDR: RORegister<u32>,
    pub GPIOC_SIDR: RORegister<u32>,
    // some fields omitted
}

Fields

GPIOC_MODER: RWRegister<u32>

GPIO port mode register

GPIOC_OTYPER: RWRegister<u32>

GPIO port output type register

GPIOC_OSPEEDR: RWRegister<u32>

GPIO port output speed register

GPIOC_PUPDR: RWRegister<u32>

GPIO port pull-up/pull-down register

GPIOC_IDR: RORegister<u32>

GPIO port input data register

GPIOC_ODR: RWRegister<u32>

GPIO port output data register

GPIOC_BSRR: WORegister<u32>

GPIO port bit set/reset register

GPIOC_LCKR: RWRegister<u32>

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

GPIOC_AFRL: RWRegister<u32>

GPIO alternate function low register

GPIOC_AFRH: RWRegister<u32>

GPIO alternate function high register

GPIOC_BRR: WORegister<u32>

GPIO port bit reset register

GPIOC_HWCFGR10: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

GPIOC_HWCFGR9: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOC_HWCFGR8: RORegister<u32>

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

GPIOC_HWCFGR7: RORegister<u32>

GPIO hardware configuration register 7

GPIOC_HWCFGR6: RORegister<u32>

GPIO hardware configuration register 6

GPIOC_HWCFGR5: RORegister<u32>

GPIO hardware configuration register 5

GPIOC_HWCFGR4: RORegister<u32>

GPIO hardware configuration register 4

GPIOC_HWCFGR3: RORegister<u32>

GPIO hardware configuration register 3

GPIOC_HWCFGR2: RORegister<u32>

GPIO hardware configuration register 2

GPIOC_HWCFGR1: RORegister<u32>

GPIO hardware configuration register 1

GPIOC_HWCFGR0: RORegister<u32>

GPIO hardware configuration register 0

GPIOC_VERR: RORegister<u32>

GPIO version register

GPIOC_IPIDR: RORegister<u32>

GPIO identification register

GPIOC_SIDR: RORegister<u32>

GPIO size identification register