Struct stm32ral::stm32mp::peripherals::gpioa::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 25 fields
pub GPIOA_MODER: RWRegister<u32>,
pub GPIOA_OTYPER: RWRegister<u32>,
pub GPIOA_OSPEEDR: RWRegister<u32>,
pub GPIOA_PUPDR: RWRegister<u32>,
pub GPIOA_IDR: RORegister<u32>,
pub GPIOA_ODR: RWRegister<u32>,
pub GPIOA_BSRR: WORegister<u32>,
pub GPIOA_LCKR: RWRegister<u32>,
pub GPIOA_AFRL: RWRegister<u32>,
pub GPIOA_AFRH: RWRegister<u32>,
pub GPIOA_BRR: WORegister<u32>,
pub GPIOA_HWCFGR10: RORegister<u32>,
pub GPIOA_HWCFGR9: RORegister<u32>,
pub GPIOA_HWCFGR8: RORegister<u32>,
pub GPIOA_HWCFGR7: RORegister<u32>,
pub GPIOA_HWCFGR6: RORegister<u32>,
pub GPIOA_HWCFGR5: RORegister<u32>,
pub GPIOA_HWCFGR4: RORegister<u32>,
pub GPIOA_HWCFGR3: RORegister<u32>,
pub GPIOA_HWCFGR2: RORegister<u32>,
pub GPIOA_HWCFGR1: RORegister<u32>,
pub GPIOA_HWCFGR0: RORegister<u32>,
pub GPIOA_VERR: RORegister<u32>,
pub GPIOA_IPIDR: RORegister<u32>,
pub GPIOA_SIDR: RORegister<u32>,
// some fields omitted
}
Fields
GPIOA_MODER: RWRegister<u32>
GPIO port mode register
GPIOA_OTYPER: RWRegister<u32>
GPIO port output type register
GPIOA_OSPEEDR: RWRegister<u32>
GPIO port output speed register
GPIOA_PUPDR: RWRegister<u32>
GPIO port pull-up/pull-down register
GPIOA_IDR: RORegister<u32>
GPIO port input data register
GPIOA_ODR: RWRegister<u32>
GPIO port output data register
GPIOA_BSRR: WORegister<u32>
GPIO port bit set/reset register
GPIOA_LCKR: RWRegister<u32>
This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).
GPIOA_AFRL: RWRegister<u32>
GPIO alternate function low register
GPIOA_AFRH: RWRegister<u32>
GPIO alternate function high register
GPIOA_BRR: WORegister<u32>
GPIO port bit reset register
GPIOA_HWCFGR10: RORegister<u32>
For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:
GPIOA_HWCFGR9: RORegister<u32>
For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
GPIOA_HWCFGR8: RORegister<u32>
For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:
GPIOA_HWCFGR7: RORegister<u32>
GPIO hardware configuration register 7
GPIOA_HWCFGR6: RORegister<u32>
GPIO hardware configuration register 6
GPIOA_HWCFGR5: RORegister<u32>
GPIO hardware configuration register 5
GPIOA_HWCFGR4: RORegister<u32>
GPIO hardware configuration register 4
GPIOA_HWCFGR3: RORegister<u32>
GPIO hardware configuration register 3
GPIOA_HWCFGR2: RORegister<u32>
GPIO hardware configuration register 2
GPIOA_HWCFGR1: RORegister<u32>
GPIO hardware configuration register 1
GPIOA_HWCFGR0: RORegister<u32>
GPIO hardware configuration register 0
GPIOA_VERR: RORegister<u32>
GPIO version register
GPIOA_IPIDR: RORegister<u32>
GPIO identification register
GPIOA_SIDR: RORegister<u32>
GPIO size identification register