Struct stm32ral::stm32mp::peripherals::eth_mtl::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 25 fields
pub ETH_MTLOMR: RWRegister<u32>,
pub ETH_MTLISR: RORegister<u32>,
pub ETH_MTLTxQ0OMR: RWRegister<u32>,
pub ETH_MTLTxQ0UR: RORegister<u32>,
pub ETH_MTLTxQ0DR: RORegister<u32>,
pub ETH_MTLTxQ0ESR: RORegister<u32>,
pub ETH_MTLQ0ICSR: RWRegister<u32>,
pub ETH_MTLRxQ0OMR: RWRegister<u32>,
pub ETH_MTLRxQ0MPOCR: RORegister<u32>,
pub ETH_MTLRxQ0DR: RORegister<u32>,
pub ETH_MTLRxQ0CR: RWRegister<u32>,
pub ETH_MTLTxQ1OMR: RWRegister<u32>,
pub ETH_MTLTxQ1UR: RORegister<u32>,
pub ETH_MTLTxQ1DR: RORegister<u32>,
pub ETH_MTLTxQ1ECR: RWRegister<u32>,
pub ETH_MTLTxQ1ESR: RORegister<u32>,
pub ETH_MTLTxQ1QWR: RWRegister<u32>,
pub ETH_MTLTxQ1SSCR: RWRegister<u32>,
pub ETH_MTLTxQ1HCR: RWRegister<u32>,
pub ETH_MTLTxQ1LCR: RWRegister<u32>,
pub ETH_MTLQ1ICSR: RWRegister<u32>,
pub ETH_MTLRxQ1OMR: RWRegister<u32>,
pub ETH_MTLRxQ1MPOCR: RORegister<u32>,
pub ETH_MTLRxQ1DR: RORegister<u32>,
pub ETH_MTLRxQ1CR: RWRegister<u32>,
// some fields omitted
}
Fields
ETH_MTLOMR: RWRegister<u32>
The Operating Mode register establishes the Transmit and Receive operating modes and commands.
ETH_MTLISR: RORegister<u32>
The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.
ETH_MTLTxQ0OMR: RWRegister<u32>
Tx queue 0 operating mode Register
ETH_MTLTxQ0UR: RORegister<u32>
Tx queue 0 underflow register
ETH_MTLTxQ0DR: RORegister<u32>
Tx queue 0 underflow register
ETH_MTLTxQ0ESR: RORegister<u32>
Tx queue x ETS status Register
ETH_MTLQ0ICSR: RWRegister<u32>
Queue 0 interrupt control status Register
ETH_MTLRxQ0OMR: RWRegister<u32>
Rx queue 0 operating mode register
ETH_MTLRxQ0MPOCR: RORegister<u32>
Rx queue 0 missed packet and overflow counter register
ETH_MTLRxQ0DR: RORegister<u32>
Rx queue i debug register
ETH_MTLRxQ0CR: RWRegister<u32>
Rx queue 0 control register
ETH_MTLTxQ1OMR: RWRegister<u32>
Tx queue 1 operating mode Register
ETH_MTLTxQ1UR: RORegister<u32>
Tx queue 1 underflow register
ETH_MTLTxQ1DR: RORegister<u32>
Tx queue 1 underflow register
ETH_MTLTxQ1ECR: RWRegister<u32>
The Queue ETS Control register controls the enhanced transmission selection operation.
ETH_MTLTxQ1ESR: RORegister<u32>
Tx queue x ETS status Register
ETH_MTLTxQ1QWR: RWRegister<u32>
This register provides the average traffic transmitted on queue 1.
ETH_MTLTxQ1SSCR: RWRegister<u32>
The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue.
ETH_MTLTxQ1HCR: RWRegister<u32>
The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue.
ETH_MTLTxQ1LCR: RWRegister<u32>
The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue.
ETH_MTLQ1ICSR: RWRegister<u32>
Queue 1 interrupt control status Register
ETH_MTLRxQ1OMR: RWRegister<u32>
Rx queue 1 operating mode register
ETH_MTLRxQ1MPOCR: RORegister<u32>
Rx queue 1 missed packet and overflow counter register
ETH_MTLRxQ1DR: RORegister<u32>
Rx queue i debug register
ETH_MTLRxQ1CR: RWRegister<u32>
Rx queue 1 control register