Struct stm32ral::stm32mp::peripherals::eth_dma::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 36 fields
pub ETH_DMAMR: RWRegister<u32>,
pub ETH_DMASBMR: RWRegister<u32>,
pub ETH_DMAISR: RORegister<u32>,
pub ETH_DMADSR: RORegister<u32>,
pub ETH_DMAA4TxACR: RWRegister<u32>,
pub ETH_DMAA4RxACR: RWRegister<u32>,
pub ETH_DMAA4DACR: RWRegister<u32>,
pub ETH_DMAC0CR: RWRegister<u32>,
pub ETH_DMAC0TxCR: RWRegister<u32>,
pub ETH_DMAC0RxCR: RWRegister<u32>,
pub ETH_DMAC0TxDLAR: RWRegister<u32>,
pub ETH_DMAC0RxDLAR: RWRegister<u32>,
pub ETH_DMAC0TxDTPR: RWRegister<u32>,
pub ETH_DMAC0RxDTPR: RWRegister<u32>,
pub ETH_DMAC0TxRLR: RWRegister<u32>,
pub ETH_DMAC0RxRLR: RWRegister<u32>,
pub ETH_DMAC0IER: RWRegister<u32>,
pub ETH_DMAC0RxIWTR: RWRegister<u32>,
pub ETH_DMAC0SFCSR: RWRegister<u32>,
pub ETH_DMAC0CATxDR: RORegister<u32>,
pub ETH_DMAC0CARxDR: RORegister<u32>,
pub ETH_DMAC0CATxBR: RORegister<u32>,
pub ETH_DMAC0CARxBR: RORegister<u32>,
pub ETH_DMAC0SR: RWRegister<u32>,
pub ETH_DMAC0MFCR: RORegister<u32>,
pub ETH_DMAC1CR: RWRegister<u32>,
pub ETH_DMAC1TxCR: RWRegister<u32>,
pub ETH_DMAC1TxDLAR: RWRegister<u32>,
pub ETH_DMAC1TxDTPR: RWRegister<u32>,
pub ETH_DMAC1TxRLR: RWRegister<u32>,
pub ETH_DMAC1IER: RWRegister<u32>,
pub ETH_DMAC1SFCSR: RWRegister<u32>,
pub ETH_DMAC1CATxDR: RORegister<u32>,
pub ETH_DMAC1CATxBR: RORegister<u32>,
pub ETH_DMAC1SR: RWRegister<u32>,
pub ETH_DMAC1MFCR: RORegister<u32>,
// some fields omitted
}
Fields
ETH_DMAMR: RWRegister<u32>
DMA mode register
ETH_DMASBMR: RWRegister<u32>
System bus mode register
ETH_DMAISR: RORegister<u32>
Interrupt status register
ETH_DMADSR: RORegister<u32>
Debug status register
ETH_DMAA4TxACR: RWRegister<u32>
AXI4 transmit channel ACE control register
ETH_DMAA4RxACR: RWRegister<u32>
AXI4 receive channel ACE control register
ETH_DMAA4DACR: RWRegister<u32>
AXI4 descriptor ACE control register
ETH_DMAC0CR: RWRegister<u32>
Channel 0 control register
ETH_DMAC0TxCR: RWRegister<u32>
Channel 0 transmit control register
ETH_DMAC0RxCR: RWRegister<u32>
Channel receive control register
ETH_DMAC0TxDLAR: RWRegister<u32>
Channel i Tx descriptor list address register
ETH_DMAC0RxDLAR: RWRegister<u32>
Channel Rx descriptor list address register
ETH_DMAC0TxDTPR: RWRegister<u32>
Channel Tx descriptor tail pointer register
ETH_DMAC0RxDTPR: RWRegister<u32>
Channel Rx descriptor tail pointer register
ETH_DMAC0TxRLR: RWRegister<u32>
Channel Tx descriptor ring length register
ETH_DMAC0RxRLR: RWRegister<u32>
Channel Rx descriptor ring length register
ETH_DMAC0IER: RWRegister<u32>
Channel interrupt enable register
ETH_DMAC0RxIWTR: RWRegister<u32>
Channel Rx interrupt watchdog timer register
ETH_DMAC0SFCSR: RWRegister<u32>
Channel i slot function control status register
ETH_DMAC0CATxDR: RORegister<u32>
Channel current application transmit descriptor register
ETH_DMAC0CARxDR: RORegister<u32>
Channel 0 current application receive descriptor register
ETH_DMAC0CATxBR: RORegister<u32>
Channel 0 current application transmit buffer register
ETH_DMAC0CARxBR: RORegister<u32>
Channel current application receive buffer register
ETH_DMAC0SR: RWRegister<u32>
Channel status register
ETH_DMAC0MFCR: RORegister<u32>
Channel missed frame count register
ETH_DMAC1CR: RWRegister<u32>
Channel 1 control register
ETH_DMAC1TxCR: RWRegister<u32>
Channel 1 transmit control register
ETH_DMAC1TxDLAR: RWRegister<u32>
Channel i Tx descriptor list address register
ETH_DMAC1TxDTPR: RWRegister<u32>
Channel Tx descriptor tail pointer register
ETH_DMAC1TxRLR: RWRegister<u32>
Channel Tx descriptor ring length register
ETH_DMAC1IER: RWRegister<u32>
Channel interrupt enable register
ETH_DMAC1SFCSR: RWRegister<u32>
Channel i slot function control status register
ETH_DMAC1CATxDR: RORegister<u32>
Channel current application transmit descriptor register
ETH_DMAC1CATxBR: RORegister<u32>
Channel 0 current application transmit buffer register
ETH_DMAC1SR: RWRegister<u32>
Channel status register
ETH_DMAC1MFCR: RORegister<u32>
Channel missed frame count register