Struct stm32ral::stm32mp::peripherals::ddrphyc::RegisterBlock[][src]

#[repr(C)]
pub struct RegisterBlock {
Show 54 fields pub DDRPHYC_RIDR: RORegister<u32>, pub DDRPHYC_PIR: WORegister<u32>, pub DDRPHYC_PGCR: RWRegister<u32>, pub DDRPHYC_PGSR: RORegister<u32>, pub DDRPHYC_DLLGCR: RWRegister<u32>, pub DDRPHYC_ACDLLCR: RWRegister<u32>, pub DDRPHYC_PTR0: RWRegister<u32>, pub DDRPHYC_PTR1: RWRegister<u32>, pub DDRPHYC_PTR2: RWRegister<u32>, pub DDRPHYC_ACIOCR: RWRegister<u32>, pub DDRPHYC_DXCCR: RWRegister<u32>, pub DDRPHYC_DSGCR: RWRegister<u32>, pub DDRPHYC_DCR: RWRegister<u32>, pub DDRPHYC_DTPR0: RWRegister<u32>, pub DDRPHYC_DTPR1: RWRegister<u32>, pub DDRPHYC_DTPR2: RWRegister<u32>, pub DDRPHYC_DDR3_MR0: RWRegister<u16>, pub DDRPHYC_DDR3_MR1: RWRegister<u16>, pub DDRPHYC_DDR3_MR2: RWRegister<u16>, pub DDRPHYC_DDR3_MR3: RWRegister<u8>, pub DDRPHYC_ODTCR: RWRegister<u32>, pub DDRPHYC_DTAR: RWRegister<u32>, pub DDRPHYC_DTDR0: RWRegister<u32>, pub DDRPHYC_DTDR1: RWRegister<u32>, pub DDRPHYC_GPR0: RWRegister<u32>, pub DDRPHYC_GPR1: RWRegister<u32>, pub DDRPHYC_ZQ0CR0: RWRegister<u32>, pub DDRPHYC_ZQ0CR1: RWRegister<u8>, pub DDRPHYC_ZQ0SR0: RORegister<u32>, pub DDRPHYC_ZQ0SR1: RORegister<u8>, pub DDRPHYC_DX0GCR: RWRegister<u32>, pub DDRPHYC_DX0GSR0: RORegister<u16>, pub DDRPHYC_DX0GSR1: RORegister<u32>, pub DDRPHYC_DX0DLLCR: RWRegister<u32>, pub DDRPHYC_DX0DQTR: RWRegister<u32>, pub DDRPHYC_DX0DQSTR: RWRegister<u32>, pub DDRPHYC_DX1GCR: RWRegister<u32>, pub DDRPHYC_DX1GSR0: RORegister<u16>, pub DDRPHYC_DX1GSR1: RORegister<u32>, pub DDRPHYC_DX1DLLCR: RWRegister<u32>, pub DDRPHYC_DX1DQTR: RWRegister<u32>, pub DDRPHYC_DX1DQSTR: RWRegister<u32>, pub DDRPHYC_DX2GCR: RWRegister<u32>, pub DDRPHYC_DX2GSR0: RORegister<u16>, pub DDRPHYC_DX2GSR1: RORegister<u32>, pub DDRPHYC_DX2DLLCR: RWRegister<u32>, pub DDRPHYC_DX2DQTR: RWRegister<u32>, pub DDRPHYC_DX2DQSTR: RWRegister<u32>, pub DDRPHYC_DX3GCR: RWRegister<u32>, pub DDRPHYC_DX3GSR0: RORegister<u16>, pub DDRPHYC_DX3GSR1: RORegister<u32>, pub DDRPHYC_DX3DLLCR: RWRegister<u32>, pub DDRPHYC_DX3DQTR: RWRegister<u32>, pub DDRPHYC_DX3DQSTR: RWRegister<u32>, // some fields omitted
}

Fields

DDRPHYC_RIDR: RORegister<u32>

DDRPHYC revision ID register

DDRPHYC_PIR: WORegister<u32>

DDRPHYC PHY initialization register

DDRPHYC_PGCR: RWRegister<u32>

DDRPHYC PHY global control register

DDRPHYC_PGSR: RORegister<u32>

DDRPHYC PHY global status register

DDRPHYC_DLLGCR: RWRegister<u32>

DDRPHYC DDR global control register

DDRPHYC_ACDLLCR: RWRegister<u32>

DDRPHYC AC DLL control register

DDRPHYC_PTR0: RWRegister<u32>

DDRPHYC PT register 0

DDRPHYC_PTR1: RWRegister<u32>

DDRPHYC PT register 1

DDRPHYC_PTR2: RWRegister<u32>

DDRPHYC PT register 2

DDRPHYC_ACIOCR: RWRegister<u32>

DDRPHYC ACIOC register

DDRPHYC_DXCCR: RWRegister<u32>

DDRPHYC DXCC register

DDRPHYC_DSGCR: RWRegister<u32>

DDRPHYC DSGC register

DDRPHYC_DCR: RWRegister<u32>

DDRPHYC DC register

DDRPHYC_DTPR0: RWRegister<u32>

DDRPHYC DTP register 0

DDRPHYC_DTPR1: RWRegister<u32>

DDRPHYC DTP register 1

DDRPHYC_DTPR2: RWRegister<u32>

DDRPHYC DTP register 2

DDRPHYC_DDR3_MR0: RWRegister<u16>

DDRPHYC MR0 register for DDR3

DDRPHYC_DDR3_MR1: RWRegister<u16>

DDRPHYC MR1 register for DDR3

DDRPHYC_DDR3_MR2: RWRegister<u16>

DDRPHYC MR2 register for DDR3

DDRPHYC_DDR3_MR3: RWRegister<u8>

DDRPHYC MR3 register for DDR3

DDRPHYC_ODTCR: RWRegister<u32>

DDRPHYC ODTC register

DDRPHYC_DTAR: RWRegister<u32>

DDRPHYC DTA register

DDRPHYC_DTDR0: RWRegister<u32>

DDRPHYC DTD register 0

DDRPHYC_DTDR1: RWRegister<u32>

DDRPHYC DTD register 1

DDRPHYC_GPR0: RWRegister<u32>

DDRPHYC general purpose register 0

DDRPHYC_GPR1: RWRegister<u32>

DDRPHYC general purpose register 1

DDRPHYC_ZQ0CR0: RWRegister<u32>

DDRPHYC ZQ0C register 0

DDRPHYC_ZQ0CR1: RWRegister<u8>

DDRPHYC ZQ0CR1 register

DDRPHYC_ZQ0SR0: RORegister<u32>

DDRPHYC ZQ0S register 0

DDRPHYC_ZQ0SR1: RORegister<u8>

DDRPHYC ZQ0S register 1

DDRPHYC_DX0GCR: RWRegister<u32>

DDRPHYC byte lane 0 GC register

DDRPHYC_DX0GSR0: RORegister<u16>

DDRPHYC byte lane 0 GS register 0

DDRPHYC_DX0GSR1: RORegister<u32>

DDRPHYC byte lane 0 GS register 1

DDRPHYC_DX0DLLCR: RWRegister<u32>

DDRPHYC byte lane 0 DLLC register

DDRPHYC_DX0DQTR: RWRegister<u32>

DDRPHYC byte lane 0 DQT register

DDRPHYC_DX0DQSTR: RWRegister<u32>

DDRPHYC byte lane 0 DQST register

DDRPHYC_DX1GCR: RWRegister<u32>

DDRPHYC byte lane 1 GC register

DDRPHYC_DX1GSR0: RORegister<u16>

DDRPHYC byte lane 1 GS register 0

DDRPHYC_DX1GSR1: RORegister<u32>

DDRPHYC byte lane 1 GS register 1

DDRPHYC_DX1DLLCR: RWRegister<u32>

DDRPHYC byte lane 1 DLLC register

DDRPHYC_DX1DQTR: RWRegister<u32>

DDRPHYC byte lane 1 DQT register

DDRPHYC_DX1DQSTR: RWRegister<u32>

DDRPHYC byte lane 1 DQST register

DDRPHYC_DX2GCR: RWRegister<u32>

DDRPHYC byte lane 2 GC register

DDRPHYC_DX2GSR0: RORegister<u16>

DDRPHYC byte lane 2 GS register 0

DDRPHYC_DX2GSR1: RORegister<u32>

DDRPHYC byte lane 2 GS register 1

DDRPHYC_DX2DLLCR: RWRegister<u32>

DDRPHYC byte lane 2 DLLC register

DDRPHYC_DX2DQTR: RWRegister<u32>

DDRPHYC byte lane 2 DQT register

DDRPHYC_DX2DQSTR: RWRegister<u32>

DDRPHYC byte lane 2 DQST register

DDRPHYC_DX3GCR: RWRegister<u32>

DDRPHYC byte lane 3 GC register

DDRPHYC_DX3GSR0: RORegister<u16>

DDRPHYC byte lane 3 GS register 0

DDRPHYC_DX3GSR1: RORegister<u32>

DDRPHYC byte lane 3 GS register 1

DDRPHYC_DX3DLLCR: RWRegister<u32>

DDRPHYC byte lane 3 DLLC register

DDRPHYC_DX3DQTR: RWRegister<u32>

DDRPHYC byte lane 3 DQT register

DDRPHYC_DX3DQSTR: RWRegister<u32>

DDRPHYC byte lane 3 DQST register

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