Struct stm32ral::stm32mp::peripherals::cryp::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {Show 40 fields
    pub CRYP_CR: RWRegister<u32>,
    pub CRYP_SR: RORegister<u32>,
    pub CRYP_DIN: RWRegister<u32>,
    pub CRYP_DOUT: RORegister<u32>,
    pub CRYP_DMACR: RWRegister<u32>,
    pub CRYP_IMSCR: RWRegister<u32>,
    pub CRYP_RISR: RORegister<u32>,
    pub CRYP_MISR: RORegister<u32>,
    pub CRYP_K0LR: WORegister<u32>,
    pub CRYP_K0RR: WORegister<u32>,
    pub CRYP_K1LR: WORegister<u32>,
    pub CRYP_K1RR: WORegister<u32>,
    pub CRYP_K2LR: WORegister<u32>,
    pub CRYP_K2RR: WORegister<u32>,
    pub CRYP_K3LR: WORegister<u32>,
    pub CRYP_K3RR: WORegister<u32>,
    pub CRYP_IV0LR: RWRegister<u32>,
    pub CRYP_IV0RR: RWRegister<u32>,
    pub CRYP_IV1LR: RWRegister<u32>,
    pub CRYP_IV1RR: RWRegister<u32>,
    pub CRYP_CSGCMCCM0R: RWRegister<u32>,
    pub CRYP_CSGCMCCM1R: RWRegister<u32>,
    pub CRYP_CSGCMCCM2R: RWRegister<u32>,
    pub CRYP_CSGCMCCM3R: RWRegister<u32>,
    pub CRYP_CSGCMCCM4R: RWRegister<u32>,
    pub CRYP_CSGCMCCM5R: RWRegister<u32>,
    pub CRYP_CSGCMCCM6R: RWRegister<u32>,
    pub CRYP_CSGCMCCM7R: RWRegister<u32>,
    pub CRYP_CSGCM0R: RWRegister<u32>,
    pub CRYP_CSGCM1R: RWRegister<u32>,
    pub CRYP_CSGCM2R: RWRegister<u32>,
    pub CRYP_CSGCM3R: RWRegister<u32>,
    pub CRYP_CSGCM4R: RWRegister<u32>,
    pub CRYP_CSGCM5R: RWRegister<u32>,
    pub CRYP_CSGCM6R: RWRegister<u32>,
    pub CRYP_CSGCM7R: RWRegister<u32>,
    pub CRYP_HWCFGR: RORegister<u32>,
    pub CRYP_VERR: RORegister<u32>,
    pub CRYP_IPIDR: RORegister<u32>,
    pub CRYP_MID: RORegister<u32>,
    // some fields omitted
}

Fields

CRYP_CR: RWRegister<u32>

CRYP control register

CRYP_SR: RORegister<u32>

CRYP status register

CRYP_DIN: RWRegister<u32>

The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.

CRYP_DOUT: RORegister<u32>

The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.

CRYP_DMACR: RWRegister<u32>

CRYP DMA control register

CRYP_IMSCR: RWRegister<u32>

The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.

CRYP_RISR: RORegister<u32>

The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.

CRYP_MISR: RORegister<u32>

The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.

CRYP_K0LR: WORegister<u32>

CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2…K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)

CRYP_K0RR: WORegister<u32>