Struct stm32ral::stm32mp::peripherals::ccu::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub FCCAN_CCU_CREL: RORegister<u32>,
    pub FCCAN_CCU_CCFG: RWRegister<u32>,
    pub FCCAN_CCU_CSTAT: RORegister<u32>,
    pub FCCAN_CCU_CWD: RWRegister<u32>,
    pub FCCAN_CCU_IR: RWRegister<u32>,
    pub FCCAN_CCU_IE: RWRegister<u32>,
}

Fields

FCCAN_CCU_CREL: RORegister<u32>

Clock calibration unit core release register

FCCAN_CCU_CCFG: RWRegister<u32>

Calibration configuration register

FCCAN_CCU_CSTAT: RORegister<u32>

Calibration status register

FCCAN_CCU_CWD: RWRegister<u32>

The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset.

FCCAN_CCU_IR: RWRegister<u32>

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not.

FCCAN_CCU_IE: RWRegister<u32>

The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line.