Struct stm32ral::stm32l5::peripherals::fmc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub FMC_BCR1: RWRegister<u32>,
    pub FMC_BTR1: RWRegister<u32>,
    pub FMC_BCR2: RWRegister<u32>,
    pub FMC_BTR2: RWRegister<u32>,
    pub FMC_BCR3: RWRegister<u32>,
    pub FMC_BTR3: RWRegister<u32>,
    pub FMC_BCR4: RWRegister<u32>,
    pub FMC_BTR4: RWRegister<u32>,
    pub PCSCNTR: RWRegister<u32>,
    pub FMC_PCR: RWRegister<u32>,
    pub FMC_SR: RWRegister<u32>,
    pub FMC_PMEM: RWRegister<u32>,
    pub FMC_PATT: RWRegister<u32>,
    pub FMC_ECCR: RORegister<u32>,
    pub FMC_BWTR1: RWRegister<u32>,
    pub FMC_BWTR2: RWRegister<u32>,
    pub FMC_BWTR3: RWRegister<u32>,
    pub FMC_BWTR4: RWRegister<u32>,
    // some fields omitted
}

Fields

FMC_BCR1: RWRegister<u32>

FMC_BCR1

FMC_BTR1: RWRegister<u32>

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

FMC_BCR2: RWRegister<u32>

FMC_BCR2

FMC_BTR2: RWRegister<u32>

FMC_BTR2

FMC_BCR3: RWRegister<u32>

FMC_BCR3

FMC_BTR3: RWRegister<u32>

FMC_BTR3

FMC_BCR4: RWRegister<u32>

FMC_BCR4

FMC_BTR4: RWRegister<u32>

FMC_BTR4

PCSCNTR: RWRegister<u32>

PCSCNTR

FMC_PCR: RWRegister<u32>

NAND Flash control registers

FMC_SR: RWRegister<u32>

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

FMC_PMEM: RWRegister<u32>

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

FMC_PATT: RWRegister<u32>

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

FMC_ECCR: RORegister<u32>

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

FMC_BWTR1: RWRegister<u32>

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

FMC_BWTR2: RWRegister<u32>

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

FMC_BWTR3: RWRegister<u32>

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

FMC_BWTR4: RWRegister<u32>

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.