Struct stm32ral::stm32l1::stm32l100::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub CR: RWRegister<u32>,
    pub ICSCR: RWRegister<u32>,
    pub CFGR: RWRegister<u32>,
    pub CIR: RWRegister<u32>,
    pub AHBRSTR: RWRegister<u32>,
    pub APB2RSTR: RWRegister<u32>,
    pub APB1RSTR: RWRegister<u32>,
    pub AHBENR: RWRegister<u32>,
    pub APB2ENR: RWRegister<u32>,
    pub APB1ENR: RWRegister<u32>,
    pub AHBLPENR: RWRegister<u32>,
    pub APB2LPENR: RWRegister<u32>,
    pub APB1LPENR: RWRegister<u32>,
    pub CSR: RWRegister<u32>,
}

Fields

CR: RWRegister<u32>

Clock control register

ICSCR: RWRegister<u32>

Internal clock sources calibration register

CFGR: RWRegister<u32>

Clock configuration register

CIR: RWRegister<u32>

Clock interrupt register

AHBRSTR: RWRegister<u32>

AHB peripheral reset register

APB2RSTR: RWRegister<u32>

APB2 peripheral reset register

APB1RSTR: RWRegister<u32>

APB1 peripheral reset register

AHBENR: RWRegister<u32>

AHB peripheral clock enable register

APB2ENR: RWRegister<u32>

APB2 peripheral clock enable register

APB1ENR: RWRegister<u32>

APB1 peripheral clock enable register

AHBLPENR: RWRegister<u32>

AHB peripheral clock enable in low power mode register

APB2LPENR: RWRegister<u32>

APB2 peripheral clock enable in low power mode register

APB1LPENR: RWRegister<u32>

APB1 peripheral clock enable in low power mode register

CSR: RWRegister<u32>

Control/status register