Struct stm32ral::stm32h7::peripherals::bdma::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 42 fields
pub ISR: RORegister<u32>,
pub IFCR: WORegister<u32>,
pub CR0: RWRegister<u32>,
pub NDTR0: RWRegister<u32>,
pub PAR0: RWRegister<u32>,
pub M0AR0: RWRegister<u32>,
pub M1AR0: RWRegister<u32>,
pub CR1: RWRegister<u32>,
pub NDTR1: RWRegister<u32>,
pub PAR1: RWRegister<u32>,
pub M0AR1: RWRegister<u32>,
pub M1AR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub NDTR2: RWRegister<u32>,
pub PAR2: RWRegister<u32>,
pub M0AR2: RWRegister<u32>,
pub M1AR2: RWRegister<u32>,
pub CR3: RWRegister<u32>,
pub NDTR3: RWRegister<u32>,
pub PAR3: RWRegister<u32>,
pub M0AR3: RWRegister<u32>,
pub M1AR3: RWRegister<u32>,
pub CR4: RWRegister<u32>,
pub NDTR4: RWRegister<u32>,
pub PAR4: RWRegister<u32>,
pub M0AR4: RWRegister<u32>,
pub M1AR4: RWRegister<u32>,
pub CR5: RWRegister<u32>,
pub NDTR5: RWRegister<u32>,
pub PAR5: RWRegister<u32>,
pub M0AR5: RWRegister<u32>,
pub M1AR5: RWRegister<u32>,
pub CR6: RWRegister<u32>,
pub NDTR6: RWRegister<u32>,
pub PAR6: RWRegister<u32>,
pub M0AR6: RWRegister<u32>,
pub M1AR6: RWRegister<u32>,
pub CR7: RWRegister<u32>,
pub NDTR7: RWRegister<u32>,
pub PAR7: RWRegister<u32>,
pub M0AR7: RWRegister<u32>,
pub M1AR7: RWRegister<u32>,
}
Fields
ISR: RORegister<u32>
DMA interrupt status register
IFCR: WORegister<u32>
DMA interrupt flag clear register
CR0: RWRegister<u32>
DMA channel x configuration register
NDTR0: RWRegister<u32>
DMA channel x number of data register
PAR0: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR0: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR0: RWRegister<u32>
Channel x memory 1 address register
CR1: RWRegister<u32>
DMA channel x configuration register
NDTR1: RWRegister<u32>
DMA channel x number of data register
PAR1: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR1: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR1: RWRegister<u32>
Channel x memory 1 address register
CR2: RWRegister<u32>
DMA channel x configuration register
NDTR2: RWRegister<u32>
DMA channel x number of data register
PAR2: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR2: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR2: RWRegister<u32>
Channel x memory 1 address register
CR3: RWRegister<u32>
DMA channel x configuration register
NDTR3: RWRegister<u32>
DMA channel x number of data register
PAR3: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR3: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR3: RWRegister<u32>
Channel x memory 1 address register
CR4: RWRegister<u32>
DMA channel x configuration register
NDTR4: RWRegister<u32>
DMA channel x number of data register
PAR4: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR4: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR4: RWRegister<u32>
Channel x memory 1 address register
CR5: RWRegister<u32>
DMA channel x configuration register
NDTR5: RWRegister<u32>
DMA channel x number of data register
PAR5: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR5: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR5: RWRegister<u32>
Channel x memory 1 address register
CR6: RWRegister<u32>
DMA channel x configuration register
NDTR6: RWRegister<u32>
DMA channel x number of data register
PAR6: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR6: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR6: RWRegister<u32>
Channel x memory 1 address register
CR7: RWRegister<u32>
DMA channel x configuration register
NDTR7: RWRegister<u32>
DMA channel x number of data register
PAR7: RWRegister<u32>
This register must not be written when the channel is enabled.
M0AR7: RWRegister<u32>
This register must not be written when the channel is enabled.
M1AR7: RWRegister<u32>
Channel x memory 1 address register