Module stm32ral::stm32h7::peripherals::bdma[−][src]

Expand description

BDMA

Used by: stm32h743, stm32h743v, stm32h747cm4, stm32h747cm7, stm32h753, stm32h753v, stm32h7b3

Modules

CR0

DMA channel x configuration register

CR1

DMA channel x configuration register

CR2

DMA channel x configuration register

CR3

DMA channel x configuration register

CR4

DMA channel x configuration register

CR5

DMA channel x configuration register

CR6

DMA channel x configuration register

CR7

DMA channel x configuration register

IFCR

DMA interrupt flag clear register

ISR

DMA interrupt status register

M0AR0

This register must not be written when the channel is enabled.

M0AR1

This register must not be written when the channel is enabled.

M0AR2

This register must not be written when the channel is enabled.

M0AR3

This register must not be written when the channel is enabled.

M0AR4

This register must not be written when the channel is enabled.

M0AR5

This register must not be written when the channel is enabled.

M0AR6

This register must not be written when the channel is enabled.

M0AR7

This register must not be written when the channel is enabled.

M1AR0

Channel x memory 1 address register

M1AR1

Channel x memory 1 address register

M1AR2

Channel x memory 1 address register

M1AR3

Channel x memory 1 address register

M1AR4

Channel x memory 1 address register

M1AR5

Channel x memory 1 address register

M1AR6

Channel x memory 1 address register

M1AR7

Channel x memory 1 address register

NDTR0

DMA channel x number of data register

NDTR1

DMA channel x number of data register

NDTR2

DMA channel x number of data register

NDTR3

DMA channel x number of data register

NDTR4

DMA channel x number of data register

NDTR5

DMA channel x number of data register

NDTR6

DMA channel x number of data register

NDTR7

DMA channel x number of data register

PAR0

This register must not be written when the channel is enabled.

PAR1

This register must not be written when the channel is enabled.

PAR2

This register must not be written when the channel is enabled.

PAR3

This register must not be written when the channel is enabled.

PAR4

This register must not be written when the channel is enabled.

PAR5

This register must not be written when the channel is enabled.

PAR6

This register must not be written when the channel is enabled.

PAR7

This register must not be written when the channel is enabled.

Structs

Instance

RegisterBlock

ResetValues