Struct stm32ral::stm32g0::peripherals::dac_v2::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 24 fields
pub DAC_CR: RWRegister<u32>,
pub DAC_SWTRGR: WORegister<u32>,
pub DAC_DHR12R1: RWRegister<u32>,
pub DAC_DHR12L1: RWRegister<u32>,
pub DAC_DHR8R1: RWRegister<u32>,
pub DAC_DHR12R2: RWRegister<u32>,
pub DAC_DHR12L2: RWRegister<u32>,
pub DAC_DHR8R2: RWRegister<u32>,
pub DAC_DHR12RD: RWRegister<u32>,
pub DAC_DHR12LD: RWRegister<u32>,
pub DAC_DHR8RD: RWRegister<u32>,
pub DAC_DOR1: RORegister<u32>,
pub DAC_DOR2: RORegister<u32>,
pub DAC_SR: RWRegister<u32>,
pub DAC_CCR: RWRegister<u32>,
pub DAC_MCR: RWRegister<u32>,
pub DAC_SHSR1: RWRegister<u32>,
pub DAC_SHSR2: RWRegister<u32>,
pub DAC_SHHR: RWRegister<u32>,
pub DAC_SHRR: RWRegister<u32>,
pub IP_HWCFGR0: RWRegister<u32>,
pub VERR: RORegister<u32>,
pub IPIDR: RORegister<u32>,
pub SIDR: RORegister<u32>,
// some fields omitted
}
Fields
DAC_CR: RWRegister<u32>
DAC control register
DAC_SWTRGR: WORegister<u32>
DAC software trigger register
DAC_DHR12R1: RWRegister<u32>
DAC channel1 12-bit right-aligned data holding register
DAC_DHR12L1: RWRegister<u32>
DAC channel1 12-bit left aligned data holding register
DAC_DHR8R1: RWRegister<u32>
DAC channel1 8-bit right aligned data holding register
DAC_DHR12R2: RWRegister<u32>
DAC channel2 12-bit right aligned data holding register
DAC_DHR12L2: RWRegister<u32>
DAC channel2 12-bit left aligned data holding register
DAC_DHR8R2: RWRegister<u32>
DAC channel2 8-bit right-aligned data holding register
DAC_DHR12RD: RWRegister<u32>
Dual DAC 12-bit right-aligned data holding register
DAC_DHR12LD: RWRegister<u32>
DUAL DAC 12-bit left aligned data holding register
DAC_DHR8RD: RWRegister<u32>
DUAL DAC 8-bit right aligned data holding register
DAC_DOR1: RORegister<u32>
DAC channel1 data output register
DAC_DOR2: RORegister<u32>
DAC channel2 data output register
DAC_SR: RWRegister<u32>
DAC status register
DAC_CCR: RWRegister<u32>
DAC calibration control register
DAC_MCR: RWRegister<u32>
DAC mode control register
DAC_SHSR1: RWRegister<u32>
DAC Sample and Hold sample time register 1
DAC_SHSR2: RWRegister<u32>
DAC Sample and Hold sample time register 2
DAC_SHHR: RWRegister<u32>
DAC Sample and Hold hold time register
DAC_SHRR: RWRegister<u32>
DAC Sample and Hold refresh time register
IP_HWCFGR0: RWRegister<u32>
DAC IP Hardware Configuration Register
VERR: RORegister<u32>
EXTI IP Version register
IPIDR: RORegister<u32>
EXTI Identification register
SIDR: RORegister<u32>
EXTI Size ID register