Struct stm32ral::stm32f4::stm32f446::sdio::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub POWER: RWRegister<u32>,
    pub CLKCR: RWRegister<u32>,
    pub ARG: RWRegister<u32>,
    pub CMD: RWRegister<u32>,
    pub RESPCMD: RORegister<u32>,
    pub RESP1: RORegister<u32>,
    pub RESP2: RORegister<u32>,
    pub RESP3: RORegister<u32>,
    pub RESP4: RORegister<u32>,
    pub DTIMER: RWRegister<u32>,
    pub DLEN: RWRegister<u32>,
    pub DCTRL: RWRegister<u32>,
    pub DCOUNT: RORegister<u32>,
    pub STA: RORegister<u32>,
    pub ICR: RWRegister<u32>,
    pub MASK: RWRegister<u32>,
    pub FIFOCNT: RORegister<u32>,
    pub FIFO: RWRegister<u32>,
    // some fields omitted
}

Fields

POWER: RWRegister<u32>

SDIO power control register

CLKCR: RWRegister<u32>

CLKCR register controls the SDIO_CK output clock.

ARG: RWRegister<u32>

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

CMD: RWRegister<u32>

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

RESPCMD: RORegister<u32>

The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).

RESP1: RORegister<u32>

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

RESP2: RORegister<u32>

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

RESP3: RORegister<u32>

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

RESP4: RORegister<u32>

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

DTIMER: RWRegister<u32>

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

DLEN: RWRegister<u32>

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

DCTRL: RWRegister<u32>

The SDMMC_DCTRL register control the data path state machine (DPSM).

DCOUNT: RORegister<u32>

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

STA: RORegister<u32>

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

ICR: RWRegister<u32>

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

MASK: RWRegister<u32>

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

FIFOCNT: RORegister<u32>

The SDIO_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.

FIFO: RWRegister<u32>

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.