Struct stm32ral::stm32f4::stm32f410::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub CR: RWRegister<u32>,
    pub PLLCFGR: RWRegister<u32>,
    pub CFGR: RWRegister<u32>,
    pub CIR: RWRegister<u32>,
    pub AHB1RSTR: RWRegister<u32>,
    pub APB1RSTR: RWRegister<u32>,
    pub APB2RSTR: RWRegister<u32>,
    pub AHB1ENR: RWRegister<u32>,
    pub APB1ENR: RWRegister<u32>,
    pub APB2ENR: RWRegister<u32>,
    pub AHB1LPENR: RWRegister<u32>,
    pub APB1LPENR: RWRegister<u32>,
    pub APB2LPENR: RWRegister<u32>,
    pub BDCR: RWRegister<u32>,
    pub CSR: RWRegister<u32>,
    pub SSCGR: RWRegister<u32>,
    pub DCKCFGR: RWRegister<u32>,
    pub DCKCFGR2: RWRegister<u32>,
    // some fields omitted
}

Fields

CR: RWRegister<u32>

clock control register

PLLCFGR: RWRegister<u32>

PLL configuration register

CFGR: RWRegister<u32>

clock configuration register

CIR: RWRegister<u32>

clock interrupt register

AHB1RSTR: RWRegister<u32>

AHB1 peripheral reset register

APB1RSTR: RWRegister<u32>

APB1 peripheral reset register

APB2RSTR: RWRegister<u32>

APB2 peripheral reset register

AHB1ENR: RWRegister<u32>

AHB1 peripheral clock register

APB1ENR: RWRegister<u32>

APB1 peripheral clock enable register

APB2ENR: RWRegister<u32>

APB2 peripheral clock enable register

AHB1LPENR: RWRegister<u32>

AHB1 peripheral clock enable in low power mode register

APB1LPENR: RWRegister<u32>

APB1 peripheral clock enable in low power mode register

APB2LPENR: RWRegister<u32>

APB2 peripheral clock enabled in low power mode register

BDCR: RWRegister<u32>

Backup domain control register

CSR: RWRegister<u32>

clock control & status register

SSCGR: RWRegister<u32>

spread spectrum clock generation register

DCKCFGR: RWRegister<u32>

DCKCFGR register

DCKCFGR2: RWRegister<u32>

DCKCFGR2 register