Struct stm32ral::stm32f0::peripherals::dma1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 30 fields
pub ISR: RORegister<u32>,
pub IFCR: WORegister<u32>,
pub CR1: RWRegister<u32>,
pub NDTR1: RWRegister<u32>,
pub PAR1: RWRegister<u32>,
pub MAR1: RWRegister<u32>,
pub CR2: RWRegister<u32>,
pub NDTR2: RWRegister<u32>,
pub PAR2: RWRegister<u32>,
pub MAR2: RWRegister<u32>,
pub CR3: RWRegister<u32>,
pub NDTR3: RWRegister<u32>,
pub PAR3: RWRegister<u32>,
pub MAR3: RWRegister<u32>,
pub CR4: RWRegister<u32>,
pub NDTR4: RWRegister<u32>,
pub PAR4: RWRegister<u32>,
pub MAR4: RWRegister<u32>,
pub CR5: RWRegister<u32>,
pub NDTR5: RWRegister<u32>,
pub PAR5: RWRegister<u32>,
pub MAR5: RWRegister<u32>,
pub CR6: RWRegister<u32>,
pub NDTR6: RWRegister<u32>,
pub PAR6: RWRegister<u32>,
pub MAR6: RWRegister<u32>,
pub CR7: RWRegister<u32>,
pub NDTR7: RWRegister<u32>,
pub PAR7: RWRegister<u32>,
pub MAR7: RWRegister<u32>,
// some fields omitted
}
Fields
ISR: RORegister<u32>
DMA interrupt status register (DMA_ISR)
IFCR: WORegister<u32>
DMA interrupt flag clear register (DMA_IFCR)
CR1: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR1: RWRegister<u32>
DMA channel 1 number of data register
PAR1: RWRegister<u32>
DMA channel 1 peripheral address register
MAR1: RWRegister<u32>
DMA channel 1 memory address register
CR2: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR2: RWRegister<u32>
DMA channel 1 number of data register
PAR2: RWRegister<u32>
DMA channel 1 peripheral address register
MAR2: RWRegister<u32>
DMA channel 1 memory address register
CR3: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR3: RWRegister<u32>
DMA channel 1 number of data register
PAR3: RWRegister<u32>
DMA channel 1 peripheral address register
MAR3: RWRegister<u32>
DMA channel 1 memory address register
CR4: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR4: RWRegister<u32>
DMA channel 1 number of data register
PAR4: RWRegister<u32>
DMA channel 1 peripheral address register
MAR4: RWRegister<u32>
DMA channel 1 memory address register
CR5: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR5: RWRegister<u32>
DMA channel 1 number of data register
PAR5: RWRegister<u32>
DMA channel 1 peripheral address register
MAR5: RWRegister<u32>
DMA channel 1 memory address register
CR6: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR6: RWRegister<u32>
DMA channel 1 number of data register
PAR6: RWRegister<u32>
DMA channel 1 peripheral address register
MAR6: RWRegister<u32>
DMA channel 1 memory address register
CR7: RWRegister<u32>
DMA channel configuration register (DMA_CCR)
NDTR7: RWRegister<u32>
DMA channel 1 number of data register
PAR7: RWRegister<u32>
DMA channel 1 peripheral address register
MAR7: RWRegister<u32>
DMA channel 1 memory address register