Struct stm32mp1::stm32mp157::sdmmc1::sdmmc_fifor11::SDMMC_FIFOR11_SPEC

pub struct SDMMC_FIFOR11_SPEC;

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see sdmmc_fifor11 module

Trait Implementations

impl Readable for SDMMC_FIFOR11_SPEC

read() method returns sdmmc_fifor11::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for SDMMC_FIFOR11_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SDMMC_FIFOR11_SPEC

reset() method sets SDMMC_FIFOR11 to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for SDMMC_FIFOR11_SPEC

write(|w| ..) method takes sdmmc_fifor11::W writer structure

type Writer = W

Writer type argument to write, et al.