Struct stm32mp1::stm32mp157::rcc::rcc_rng1ckselr::RCC_RNG1CKSELR_SPEC

pub struct RCC_RNG1CKSELR_SPEC;

This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see rcc_rng1ckselr module

Trait Implementations

impl Readable for RCC_RNG1CKSELR_SPEC

read() method returns rcc_rng1ckselr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for RCC_RNG1CKSELR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for RCC_RNG1CKSELR_SPEC

reset() method sets RCC_RNG1CKSELR to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for RCC_RNG1CKSELR_SPEC

write(|w| ..) method takes rcc_rng1ckselr::W writer structure

type Writer = W

Writer type argument to write, et al.