Struct stm32mp1::stm32mp157::fmc::fmc_pcscntr::FMC_PCSCNTR_SPEC

pub struct FMC_PCSCNTR_SPEC;

This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see fmc_pcscntr module

Trait Implementations

impl Readable for FMC_PCSCNTR_SPEC

read() method returns fmc_pcscntr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for FMC_PCSCNTR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FMC_PCSCNTR_SPEC

reset() method sets FMC_PCSCNTR to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FMC_PCSCNTR_SPEC

write(|w| ..) method takes fmc_pcscntr::W writer structure

type Writer = W

Writer type argument to write, et al.