Struct stm32mp1::stm32mp157::fdcan1::fdcan_rwd::FDCAN_RWD_SPEC

pub struct FDCAN_RWD_SPEC;

The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see fdcan_rwd module

Trait Implementations

impl Readable for FDCAN_RWD_SPEC

read() method returns fdcan_rwd::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for FDCAN_RWD_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FDCAN_RWD_SPEC

reset() method sets FDCAN_RWD to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FDCAN_RWD_SPEC

write(|w| ..) method takes fdcan_rwd::W writer structure

type Writer = W

Writer type argument to write, et al.