Struct stm32mp1::stm32mp157::fdcan1::fdcan_dbtp::FDCAN_DBTP_SPEC

pub struct FDCAN_DBTP_SPEC;

This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see fdcan_dbtp module

Trait Implementations

impl Readable for FDCAN_DBTP_SPEC

read() method returns fdcan_dbtp::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for FDCAN_DBTP_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FDCAN_DBTP_SPEC

reset() method sets FDCAN_DBTP to value 0x0a33

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FDCAN_DBTP_SPEC

write(|w| ..) method takes fdcan_dbtp::W writer structure

type Writer = W

Writer type argument to write, et al.