Struct stm32mp1::stm32mp157::eth_mac_mmc::eth_macssir::ETH_MACSSIR_SPEC

pub struct ETH_MACSSIR_SPEC;

The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see eth_macssir module

Trait Implementations

impl Readable for ETH_MACSSIR_SPEC

read() method returns eth_macssir::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for ETH_MACSSIR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for ETH_MACSSIR_SPEC

reset() method sets ETH_MACSSIR to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for ETH_MACSSIR_SPEC

write(|w| ..) method takes eth_macssir::W writer structure

type Writer = W

Writer type argument to write, et al.