Struct stm32mp1::stm32mp157::eth_mac_mmc::eth_macht0r::ETH_MACHT0R_SPEC

pub struct ETH_MACHT0R_SPEC;

The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see eth_macht0r module

Trait Implementations

impl Readable for ETH_MACHT0R_SPEC

read() method returns eth_macht0r::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for ETH_MACHT0R_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for ETH_MACHT0R_SPEC

reset() method sets ETH_MACHT0R to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for ETH_MACHT0R_SPEC

write(|w| ..) method takes eth_macht0r::W writer structure

type Writer = W

Writer type argument to write, et al.