Struct stm32mp1::stm32mp157::eth_mac_mmc::eth_maca0hr::ETH_MACA0HR_SPEC

pub struct ETH_MACA0HR_SPEC;

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see eth_maca0hr module

Trait Implementations

impl Readable for ETH_MACA0HR_SPEC

read() method returns eth_maca0hr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for ETH_MACA0HR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for ETH_MACA0HR_SPEC

reset() method sets ETH_MACA0HR to value 0x8000_ffff

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for ETH_MACA0HR_SPEC

write(|w| ..) method takes eth_maca0hr::W writer structure

type Writer = W

Writer type argument to write, et al.