[−][src]Struct stm32mp1::stm32mp157::tim3::RegisterBlock

[+] Show declaration

[+] Expand attributes
#[repr(C)]pub struct RegisterBlock {
    pub tim3_cr1: TIM3_CR1,
    pub tim3_cr2: TIM3_CR2,
    pub tim3_smcr: TIM3_SMCR,
    pub tim3_dier: TIM3_DIER,
    pub tim3_sr: TIM3_SR,
    pub tim3_egr: TIM3_EGR,
    pub tim3_ccmr1alternate3: TIM3_CCMR1ALTERNATE3,
    pub tim3_ccmr2alternate19: TIM3_CCMR2ALTERNATE19,
    pub tim3_ccer: TIM3_CCER,
    pub tim3_cnt: TIM3_CNT,
    pub tim3_psc: TIM3_PSC,
    pub tim3_arr: TIM3_ARR,
    pub tim3_rcr: TIM3_RCR,
    pub tim3_ccr1: TIM3_CCR1,
    pub tim3_ccr2: TIM3_CCR2,
    pub tim3_ccr3: TIM3_CCR3,
    pub tim3_ccr4: TIM3_CCR4,
    pub tim3_bdtr: TIM3_BDTR,
    pub tim3_dcr: TIM3_DCR,
    pub tim3_dmar: TIM3_DMAR,
    pub tim3_ccmr3: TIM3_CCMR3,
    pub tim3_ccr5: TIM3_CCR5,
    pub tim3_ccr6: TIM3_CCR6,
    // some fields omitted
}

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Register block

Fields

tim3_cr1: TIM3_CR1

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0x00 - TIM3 control register 1

tim3_cr2: TIM3_CR2

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0x04 - TIM3 control register 2

tim3_smcr: TIM3_SMCR

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0x08 - TIM3 slave mode control register

tim3_dier: TIM3_DIER

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0x0c - TIM3 DMA/interrupt enable register

tim3_sr: TIM3_SR

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0x10 - TIM3 status register

tim3_egr: TIM3_EGR

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0x14 - TIM3 event generation register

tim3_ccmr1alternate3: TIM3_CCMR1ALTERNATE3

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0x18 - The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

tim3_ccmr2alternate19: TIM3_CCMR2ALTERNATE19

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0x1c - The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

tim3_ccer: TIM3_CCER

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0x20 - TIM3 capture/compare enable register

tim3_cnt: TIM3_CNT

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0x24 - TIM3 counter

tim3_psc: TIM3_PSC

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0x28 - TIM3 prescaler

tim3_arr: TIM3_ARR

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0x2c - TIM3 auto-reload register

tim3_rcr: TIM3_RCR

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0x30 - TIM3 repetition counter register

tim3_ccr1: TIM3_CCR1

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0x34 - TIM3 capture/compare register 1

tim3_ccr2: TIM3_CCR2

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0x38 - TIM3 capture/compare register 2

tim3_ccr3: TIM3_CCR3

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0x3c - TIM3 capture/compare register 3

tim3_ccr4: TIM3_CCR4

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0x40 - TIM3 capture/compare register 4

tim3_bdtr: TIM3_BDTR

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0x44 - As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

tim3_dcr: TIM3_DCR

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0x48 - TIM3 DMA control register

tim3_dmar: TIM3_DMAR

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0x4c - TIM3 DMA address for full transfer

tim3_ccmr3: TIM3_CCMR3

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0x54 - The channels 5 and 6 can only be configured in output. Output compare mode:

tim3_ccr5: TIM3_CCR5

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0x58 - TIM3 capture/compare register 5