DmaInput

stm32l4xx_hal::dmamux

Enum DmaInput

pub enum DmaInput {
Show 99 variants    Generator0,
    Generator1,
    Generator2,
    Generator3,
    Adc1,
    Adc2,
    Adc3,
    Dac1Ch1,
    Dac1Ch2,
    Spi1Rx,
    Spi1Tx,
    Spi2Rx,
    Spi2Tx,
    Spi3Rx,
    Spi3Tx,
    I2c1Rx,
    I2c1Tx,
    I2c2Rx,
    I2c2Tx,
    I2c3Rx,
    I2c3Tx,
    I2c4Rx,
    I2c4Tx,
    Usart1Rx,
    Usart1Tx,
    Usart2Rx,
    Usart2Tx,
    Usart3Rx,
    Usart3Tx,
    Uart4Rx,
    Uart4Tx,
    Uart5Rx,
    Uart5Tx,
    LpUart1Rx,
    LpUart1Tx,
    Sai1A,
    Sai1B,
    Sai2A,
    Sai2B,
    QuadSpi,
    OctoSpi1,
    OctoSpi2,
    Tim6Up,
    Tim7Up,
    Tim1Ch1,
    Tim1Ch2,
    Tim1Ch3,
    Tim1Ch4,
    Tim1Up,
    Tim1Trig,
    Tim1Com,
    Tim8Ch1,
    Tim8Ch2,
    Tim8Ch3,
    Tim8Ch4,
    Tim8Up,
    Tim8Trig,
    Tim8Com,
    Tim2Ch1,
    Tim2Ch2,
    Tim2Ch3,
    Tim2Ch4,
    Tim2Up,
    Tim3Ch1,
    Tim3Ch2,
    Tim3Ch3,
    Tim3Ch4,
    Tim3Up,
    Tim3Trig,
    Tim4Ch1,
    Tim4Ch2,
    Tim4Ch3,
    Tim4Ch4,
    Tim4Up,
    Tim5Ch1,
    Tim5Ch2,
    Tim5Ch3,
    Tim5Ch4,
    Tim5Up,
    Tim5Trig,
    Tim15Ch1,
    Tim15Up,
    Tim15Trig,
    Tim15Com,
    Tim16Ch1,
    Tim16Up,
    Tim17Ch1,
    Tim17Up,
    Dfsdm1Flt0,
    Dfsdm1Flt1,
    Dfsdm1Flt2,
    Dfsdm1Flt3,
    Dcmi,
    AesIn,
    AesOut,
    HashIn,
    Swpmi1Rx,
    Swpmi1Tx,
    SdMmc1,
}

Expand description

Input DMA request line selected

Variants§

Generator0

Generator1

Generator2

Generator3

Adc1

Adc2

Adc3

Dac1Ch1

Dac1Ch2

Spi1Rx

Spi1Tx

Spi2Rx

Spi2Tx

Spi3Rx

Spi3Tx

I2c1Rx

I2c1Tx

I2c2Rx

I2c2Tx

I2c3Rx

I2c3Tx

I2c4Rx

I2c4Tx

Usart1Rx

Usart1Tx

Usart2Rx

Usart2Tx

Usart3Rx

Usart3Tx

Uart4Rx

Uart4Tx

Uart5Rx

Uart5Tx

LpUart1Rx

LpUart1Tx

Sai1A

Sai1B

Sai2A

Sai2B

QuadSpi

OctoSpi1

OctoSpi2

Tim6Up

Tim7Up

Tim1Ch1

Tim1Ch2

Tim1Ch3

Tim1Ch4

Tim1Up

Tim1Trig

Tim1Com

Tim8Ch1

Tim8Ch2

Tim8Ch3

Tim8Ch4

Tim8Up

Tim8Trig

Tim8Com

Tim2Ch1

Tim2Ch2

Tim2Ch3

Tim2Ch4

Tim2Up

Tim3Ch1

Tim3Ch2

Tim3Ch3

Tim3Ch4

Tim3Up

Tim3Trig

Tim4Ch1

Tim4Ch2

Tim4Ch3

Tim4Ch4

Tim4Up

Tim5Ch1

Tim5Ch2

Tim5Ch3

Tim5Ch4

Tim5Up

Tim5Trig

Tim15Ch1

Tim15Up

Tim15Trig

Tim15Com

Tim16Ch1

Tim16Up

Tim17Ch1

Tim17Up

Dfsdm1Flt0

Dfsdm1Flt1

Dfsdm1Flt2

Dfsdm1Flt3

Dcmi

AesIn

AesOut

HashIn

Swpmi1Rx

Swpmi1Tx

SdMmc1

Auto Trait Implementations§

impl Freeze for DmaInput

impl RefUnwindSafe for DmaInput

impl Send for DmaInput

impl Sync for DmaInput

impl Unpin for DmaInput

impl UnwindSafe for DmaInput

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.