Struct CFGR 

pub struct CFGR { /* private fields */ }

Clock configuration

Implementations

impl CFGR

pub fn hse( self, freq: Hertz, bypass: CrystalBypass, css: ClockSecuritySystem, ) -> Self

Add an HSE to the system

pub fn lse(self, bypass: CrystalBypass, css: ClockSecuritySystem) -> Self

Add an 32.768 kHz LSE to the system

pub fn hclk(self, freq: Hertz) -> Self

Sets a frequency for the AHB bus

pub fn hsi48(self, on: bool) -> Self

Enable the 48 MHz USB, RNG, SDMMC HSI clock source. Not available on all stm32l4x6 series

pub fn msi(self, range: MsiFreq) -> Self

Enables the MSI with the specified speed

pub fn lsi(self, on: bool) -> Self

Sets LSI clock on (the default) or off

pub fn pclk1(self, freq: Hertz) -> Self

Sets a frequency for the APB1 bus

pub fn pclk2(self, freq: Hertz) -> Self

Sets a frequency for the APB2 bus

pub fn sysclk(self, freq: Hertz) -> Self

Sets the system (core) frequency

pub fn sysclk_with_pll(self, freq: Hertz, cfg: PllConfig) -> Self

Sets the system (core) frequency with some pll configuration

pub fn pll_source(self, source: PllSource) -> Self

Sets the PLL source

pub fn freeze(&self, acr: &mut ACR, pwr: &mut Pwr) -> Clocks

Freezes the clock configuration, making it effective