[−][src]Struct stm32l4xx_hal::stm32::dac1::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub swtrigr: Reg<u32, _SWTRIGR>,
    pub dhr12r1: Reg<u32, _DHR12R1>,
    pub dhr12l1: Reg<u32, _DHR12L1>,
    pub dhr8r1: Reg<u32, _DHR8R1>,
    pub dhr12r2: Reg<u32, _DHR12R2>,
    pub dhr12l2: Reg<u32, _DHR12L2>,
    pub dhr8r2: Reg<u32, _DHR8R2>,
    pub dhr12rd: Reg<u32, _DHR12RD>,
    pub dhr12ld: Reg<u32, _DHR12LD>,
    pub dhr8rd: Reg<u32, _DHR8RD>,
    pub dor1: Reg<u32, _DOR1>,
    pub dor2: Reg<u32, _DOR2>,
    pub sr: Reg<u32, _SR>,
    pub ccr: Reg<u32, _CCR>,
    pub mcr: Reg<u32, _MCR>,
    pub shsr1: Reg<u32, _SHSR1>,
    pub shsr2: Reg<u32, _SHSR2>,
    pub shhr: Reg<u32, _SHHR>,
    pub shrr: Reg<u32, _SHRR>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - control register

swtrigr: Reg<u32, _SWTRIGR>

0x04 - software trigger register

dhr12r1: Reg<u32, _DHR12R1>

0x08 - channel1 12-bit right-aligned data holding register

dhr12l1: Reg<u32, _DHR12L1>

0x0c - channel1 12-bit left-aligned data holding register

dhr8r1: Reg<u32, _DHR8R1>

0x10 - channel1 8-bit right-aligned data holding register

dhr12r2: Reg<u32, _DHR12R2>

0x14 - channel2 12-bit right aligned data holding register

dhr12l2: Reg<u32, _DHR12L2>

0x18 - channel2 12-bit left aligned data holding register

dhr8r2: Reg<u32, _DHR8R2>

0x1c - channel2 8-bit right-aligned data holding register

dhr12rd: Reg<u32, _DHR12RD>

0x20 - Dual DAC 12-bit right-aligned data holding register

dhr12ld: Reg<u32, _DHR12LD>

0x24 - DUAL DAC 12-bit left aligned data holding register

dhr8rd: Reg<u32, _DHR8RD>

0x28 - DUAL DAC 8-bit right aligned data holding register

dor1: Reg<u32, _DOR1>

0x2c - channel1 data output register

dor2: Reg<u32, _DOR2>

0x30 - channel2 data output register

sr: Reg<u32, _SR>

0x34 - status register

ccr: Reg<u32, _CCR>

0x38 - calibration control register

mcr: Reg<u32, _MCR>

0x3c - mode control register

shsr1: Reg<u32, _SHSR1>

0x40 - Sample and Hold sample time register 1

shsr2: Reg<u32, _SHSR2>

0x44 - Sample and Hold sample time register 2

shhr: Reg<u32, _SHHR>

0x48 - Sample and Hold hold time register

shrr: Reg<u32, _SHRR>

0x4c - Sample and Hold refresh time register

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.