Struct stm32l4x6::rcc::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 30 fields
pub cr: CR,
pub icscr: ICSCR,
pub cfgr: CFGR,
pub pllcfgr: PLLCFGR,
pub pllsai1cfgr: PLLSAI1CFGR,
pub pllsai2cfgr: PLLSAI2CFGR,
pub cier: CIER,
pub cifr: CIFR,
pub cicr: CICR,
pub ahb1rstr: AHB1RSTR,
pub ahb2rstr: AHB2RSTR,
pub ahb3rstr: AHB3RSTR,
pub apb1rstr1: APB1RSTR1,
pub apb1rstr2: APB1RSTR2,
pub apb2rstr: APB2RSTR,
pub ahb1enr: AHB1ENR,
pub ahb2enr: AHB2ENR,
pub ahb3enr: AHB3ENR,
pub apb1enr1: APB1ENR1,
pub apb1enr2: APB1ENR2,
pub apb2enr: APB2ENR,
pub ahb1smenr: AHB1SMENR,
pub ahb2smenr: AHB2SMENR,
pub ahb3smenr: AHB3SMENR,
pub apb1smenr1: APB1SMENR1,
pub apb1smenr2: APB1SMENR2,
pub apb2smenr: APB2SMENR,
pub ccipr: CCIPR,
pub bdcr: BDCR,
pub csr: CSR,
/* private fields */
}
Expand description
Register block
Fields§
§cr: CR
0x00 - Clock control register
icscr: ICSCR
0x04 - Internal clock sources calibration register
cfgr: CFGR
0x08 - Clock configuration register
pllcfgr: PLLCFGR
0x0c - PLL configuration register
pllsai1cfgr: PLLSAI1CFGR
0x10 - PLLSAI1 configuration register
pllsai2cfgr: PLLSAI2CFGR
0x14 - PLLSAI2 configuration register
cier: CIER
0x18 - Clock interrupt enable register
cifr: CIFR
0x1c - Clock interrupt flag register
cicr: CICR
0x20 - Clock interrupt clear register
ahb1rstr: AHB1RSTR
0x28 - AHB1 peripheral reset register
ahb2rstr: AHB2RSTR
0x2c - AHB2 peripheral reset register
ahb3rstr: AHB3RSTR
0x30 - AHB3 peripheral reset register
apb1rstr1: APB1RSTR1
0x38 - APB1 peripheral reset register 1
apb1rstr2: APB1RSTR2
0x3c - APB1 peripheral reset register 2
apb2rstr: APB2RSTR
0x40 - APB2 peripheral reset register
ahb1enr: AHB1ENR
0x48 - AHB1 peripheral clock enable register
ahb2enr: AHB2ENR
0x4c - AHB2 peripheral clock enable register
ahb3enr: AHB3ENR
0x50 - AHB3 peripheral clock enable register
apb1enr1: APB1ENR1
0x58 - APB1ENR1
apb1enr2: APB1ENR2
0x5c - APB1 peripheral clock enable register 2
apb2enr: APB2ENR
0x60 - APB2ENR
ahb1smenr: AHB1SMENR
0x68 - AHB1 peripheral clocks enable in Sleep and Stop modes register
ahb2smenr: AHB2SMENR
0x6c - AHB2 peripheral clocks enable in Sleep and Stop modes register
ahb3smenr: AHB3SMENR
0x70 - AHB3 peripheral clocks enable in Sleep and Stop modes register
apb1smenr1: APB1SMENR1
0x78 - APB1SMENR1
apb1smenr2: APB1SMENR2
0x7c - APB1 peripheral clocks enable in Sleep and Stop modes register 2
apb2smenr: APB2SMENR
0x80 - APB2SMENR
ccipr: CCIPR
0x88 - CCIPR
bdcr: BDCR
0x90 - BDCR
csr: CSR
0x94 - CSR