Struct stm32l4x6::adc1::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub isr: ISR, pub ier: IER, pub cr: CR, pub cfgr: CFGR, pub cfgr2: CFGR2, pub smpr1: SMPR1, pub smpr2: SMPR2, pub tr1: TR1, pub tr2: TR2, pub tr3: TR3, pub sqr1: SQR1, pub sqr2: SQR2, pub sqr3: SQR3, pub sqr4: SQR4, pub dr: DR, pub jsqr: JSQR, pub ofr1: OFR1, pub ofr2: OFR2, pub ofr3: OFR3, pub ofr4: OFR4, pub jdr1: JDR1, pub jdr2: JDR2, pub jdr3: JDR3, pub jdr4: JDR4, pub awd2cr: AWD2CR, pub awd3cr: AWD3CR, pub difsel: DIFSEL, pub calfact: CALFACT, // some fields omitted }
Register block
Fields
isr: ISR
0x00 - interrupt and status register
ier: IER
0x04 - interrupt enable register
cr: CR
0x08 - control register
cfgr: CFGR
0x0c - configuration register
cfgr2: CFGR2
0x10 - configuration register
smpr1: SMPR1
0x14 - sample time register 1
smpr2: SMPR2
0x18 - sample time register 2
tr1: TR1
0x20 - watchdog threshold register 1
tr2: TR2
0x24 - watchdog threshold register
tr3: TR3
0x28 - watchdog threshold register 3
sqr1: SQR1
0x30 - regular sequence register 1
sqr2: SQR2
0x34 - regular sequence register 2
sqr3: SQR3
0x38 - regular sequence register 3
sqr4: SQR4
0x3c - regular sequence register 4
dr: DR
0x40 - regular Data Register
jsqr: JSQR
0x4c - injected sequence register
ofr1: OFR1
0x60 - offset register 1
ofr2: OFR2
0x64 - offset register 2
ofr3: OFR3
0x68 - offset register 3
ofr4: OFR4
0x6c - offset register 4
jdr1: JDR1
0x80 - injected data register 1
jdr2: JDR2
0x84 - injected data register 2
jdr3: JDR3
0x88 - injected data register 3
jdr4: JDR4
0x8c - injected data register 4
awd2cr: AWD2CR
0xa0 - Analog Watchdog 2 Configuration Register
awd3cr: AWD3CR
0xa4 - Analog Watchdog 3 Configuration Register
difsel: DIFSEL
0xb0 - Differential Mode Selection Register 2
calfact: CALFACT
0xb4 - Calibration Factors